21.   USART im SPI-Modus

21.1   Features

• Vollduplex, Synchroner Datentransfer mit drei Leitungen
• Master-Betrieb „MSPIM“
• Unterstützt alle vier SPI-Modi (Modus 0, 1, 2 und 3)
• LSB oder MSB zuerst (konfigurierbare Bitreihenfolge)
• Doppelt gepufferte Datenwarteschlange
• Hohe Auflösung des Baudratengenerators
• Hochgeschwindigkeits-Betriebsmodus (f_XCKmax = f_CK/2)
• Flexible Interrupterzeugung

21.2   Übersicht

21.3   Takterzeugung

21.4   SPI-Datenmodi und -Zeiten

Bild 21-1: Zeitdiagramme für die vier Kombinationen aus UCPHAn und UCPOLn

21.5   Rahmenformate

• 8 Bit Data mit MSB zuerst
• 8 Bit Data mit LSB zuerst

21.5.1.   MSPIM-Initialisierung

Note:

To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be zero at the time the transmitter is enabled. Contrary to the normal mode USART operation the UBRRn must then be written to the desired value after the transmitter is enabled, but before the first transmission is started. Setting UBRRn to zero before enabling the transmitter is not necessary if the initialization is done immediately after a reset since UBRRn is reset to zero.

USART_Init:
	clr  r18
	out  UBRRnH,r18
	out  UBRRnL,r18
; Das XCKn-Portpin als Ausgang setzen, was den Master-Modus aktiviert
	sbi  XCKn_DDR, XCKn
; MSPI-Betriebsart auf SPI-Modus 0 setzen
	ldi  r18,(1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)
	out  UCSRnC,r18
; Sender und Empfänger freigeben
	ldi  r18,(1<<RXENn)|(1<<TXENn)
	out  UCSRnB,r18
; Baudrate setzen.
; WICHTIG: Die Baudrate darf erst nach der Aktivierung von Sender und Empfänger gesetzt werden!
	out  UBRRnH,r17
	out  UBRRnL,r18
	ret

void USART_Init(unsigned int baud) {
  UBRRn = 0;
/* Das XCKn-Portpin als Ausgang setzen, was den Master-Modus aktiviert */
  XCKn_DDR |= (1<<XCKn);
/* MSPI-Betriebsart auf SPI-Modus 0 setzen */
  UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn);
/* Sender und Empfänger freigeben */
  UCSRnB = (1<<RXENn)|(1<<TXENn);
/* Baudrate setzen. */
/* WICHTIG: Die Baudrate darf erst nach der Aktivierung von Sender und Empfänger gesetzt werden! */
  UBRRn = baud;
}

21.6   Datentransfer

After initialization the USART is ready for doing data transfers. A data transfer is initiated by writing to the UDRn I/O location. This is the case for both sending and receiving data since the transmitter controls the transfer clock. The data written to UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send a new frame.

Note:

To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must be read once for each byte transmitted. The input buffer operation is identical to normal USART mode, i.e. if an overflow occurs the character last received will be lost, not the first data in the buffer. This means that if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and the UDRn is not read before all transfers are completed, then byte 3 to be received will be lost, and not byte 1.

The function simply waits for the transmit buffer to be empty by checking the UDREn Flag, before loading it with new data to be transmitted. The function then waits for data to be present in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the value.

USART_MSPIM_Transfer:
; Wait for empty transmit buffer
	in r16, UCSRnA
	sbrs r16, UDREn
	rjmp USART_MSPIM_Transfer
; Put data (r16) into buffer, sends the data
	out UDRn,r16
; Wait for data to be received
	USART_MSPIM_Wait_RXCn:
	in r16, UCSRnA
	sbrs r16, RXCn
	rjmp USART_MSPIM_Wait_RXCn
; Get and return received data from buffer
	in r16, UDRn
	ret

unsigned char USART_Receive( void )
{
/* Wait for empty transmit buffer */
  while ( !( UCSRnA & (1<<UDREn)) );
/* Put data into buffer, sends the data */
  UDRn = data;
/* Wait for data to be received */
  while ( !(UCSRnA & (1<<RXCn)) );
/* Get and return received data from buffer */
  return UDRn;
}

21.6.1   Sende- und Empfängerflags und Interrupts

21.6.2   Deaktivierung des Senders oder Empfängers

21.7   Gegenüberstellung MSPIM und SPI

• Master mode timing diagram.
• The UCPOLn bit functionality is identical to the SPI CPOL bit.
• The UCPHAn bit functionality is identical to the SPI CPHA bit.
• The UDORDn bit functionality is identical to the SPI DORD bit.

• The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no buffer.
• The USART in MSPIM mode receiver includes an additional buffer level.
• The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode.
• The SPI double speed mode (SPI2X) bit is not included. However, the same effect is achieved by setting UBRRn accordingly.
• Interrupt timing is not compatible.
• Pin control differs due to the master only operation of the USART in MSPIM mode.

21.8   Register-Beschreibung

21.8.1   UDRn — Bidirektionales Datenregister

21.8.2   UCSRnA — Kontroll- und Statusregister A