#include "Settings.h"
#include <F2837xD_sdfm_drivers.h> // Nur noch Bitfeld-Konstanten
#include "regdef2.h"
/*-----------------------------------------------------------------------------
* Sigma Delta Filter Module - frame setting
* ----------------------------------------------------------------------------
*/
const int SDFM_TICKS = F_CPU/2/20E6; // /2 wegen Vorteiler für ePWM, 20E6 = 20 MHz
// Der PWM-Generator eignet sich per se nicht so recht,
// 20 MHz (für die AMC1204) mit Tastverhältnisabweichung < 5 % zu produzieren:
// 100 MHz = 10-ns-Stückelung würden 20 ns High-Pegel und 30 ns Low-Pegel ergeben.
// Auch der „Micro Edge Positioner“ (MEP) funktioniert nicht,
// weil die Takte < 3 Impulse vom Start entfernt liegt.
// Was geht ist der Totzeitgenerator im Modus „Halbzyklus“.
const int OSR_RATE = OSR_128;
#ifdef CPU1
# define SdfmRegs Sdfm1RegsA // CPU1 bekommt SDFM1
#else
# define SdfmRegs Sdfm2RegsA // CPU2 bekommt SDFM2
#endif
//SD Trip Level - scope for additonal work
static const Uint16
HLT = 0x7FFF,
LLT = 0x0;
static const float SD_PU_SCALE_FACTOR = 1.0/32768;
static const float SDFM_TO_SHUNT = 1.41131; // (12.5/0.8906)/9.945
static float offsetSDFM[2]; // offset in SD current V/W fbk channel @ 0A
void Currentsense::readSDFM() {
As = (SdfmRegs.A[0].UH16*SD_PU_SCALE_FACTOR - offsetSDFM[0]) * SDFM_TO_SHUNT;
Bs = (SdfmRegs.A[1].UH16*SD_PU_SCALE_FACTOR - offsetSDFM[1]) * SDFM_TO_SHUNT;
Cs = -As -Bs;
}
void Currentsense::integrateSDFMoffset(float K2) {
float K1=1-K2;
offsetSDFM[0] = K1*offsetSDFM[0] + K2*SdfmRegs.A[0].UH16*SD_PU_SCALE_FACTOR;
offsetSDFM[1] = K1*offsetSDFM[1] + K2*SdfmRegs.A[1].UH16*SD_PU_SCALE_FACTOR;
}
void Currentsense::resetSDFMoffset() {
offsetSDFM[1]=offsetSDFM[0]=0;
}
void initSigmaDelta() {
// Setup GPIO for SD current measurement
// Pullups sind aus unter der Annahme, dass tatsächlich ΣΔ-Konverter angeschlossen sind
// und ggf. der Mikrocontroller als Taktquelle zurückgeführt ist (beim AMC1204)
#ifdef CPU1
configGpio(122,7,3); // SD1_S1 (3 = asynchron)
configGpio(123,7,3); // SD1_C1
configGpio(124,7,3); // SD1_D2
configGpio(125,7,3); // SD1_C2
configGpio(130,7,3); // SD2_D1
configGpio(131,7,3); // SD2_C1
configGpio(26,7,3); // SD2_D2
configGpio(27,7,3); // SD2_C2
configGpio(16,5,0); // ePWM9A
// Setup GPIO for SD voltage measurement
// configGpio(60,7,3); // SD2_D3
// configGpio(61,7,3); // SD2_C3
// 20 MHz clock output on GPIO15
configGpio(15,1,0); // ePWM8B
// Sigma Delta clock set up - pwm8 — 20 Mhz => 50ns => 50ns/10
configPwm(EPwm8Regs,SDFM_TICKS,0);
EPwm8Regs.CMPA.bit.CMPA = (SDFM_TICKS+1)/2;
DBCTL_REG dbctl = {0};
dbctl.bit.HALFCYCLE = 1;
dbctl.bit.OUTSWAP = 0b11; // A und B einfach vertauschen
dbctl.bit.OUT_MODE = 0b11;
EPwm8Regs.DBCTL.all = dbctl.all;
if (SDFM_TICKS&1) EPwm8Regs.DBRED=1; // Steigende Flanke ½ Takt verzögern
// Sigma Delta clock set up - pwm9 — 20 Mhz => 50ns => 50ns/10
configPwm(EPwm9Regs,SDFM_TICKS,0);
EPwm9Regs.CMPA.bit.CMPA = (SDFM_TICKS+1)/2;
if (SDFM_TICKS&1) { // Wenn ungerade …
DBCTL_REG dbctl = {0};
dbctl.bit.HALFCYCLE = 1;
dbctl.bit.OUT_MODE = 0b11;
EPwm9Regs.DBCTL.all = dbctl.all;
EPwm9Regs.DBRED = 1; // Steigende Flanke ½ Takt verzögern
}
const int nChannels = 2; // nur Kanäle 1 und 2 nutzbar
#else
const int nChannels = 3; // auch Kanal 3 nutzbar (4 nicht)
#endif
for (int i=0; i<nChannels; i++) {
/************************/
/* Input Control Module */
/************************/
//Configure Input Control Mode: Modulator Clock rate = Modulator data rate
SdfmRegs[i].CTLPARM.bit.MOD = MODE_0;
/*********************/
/* Comparator Module */
/*********************/
//Comparator HLT and LLT
//Configure Comparator module's comparator filter type and comparator's OSR value,
// high level threshold, low level threshold
SdfmRegs[i].CPARM.bit.CS1_CS0 = SINC3;
SdfmRegs[i].CPARM.bit.COSR = OSR_32;
SdfmRegs[i].CMPH.bit.HLT = HLT;
SdfmRegs[i].CMPL.bit.LLT = LLT;
/**********************/
/* Sinc filter Module */
/**********************/
//Configure Data filter modules filter type, OSR value and enable / disable data filter
// 16 bit data representation is chosen for OSR 128 using Sinc3, from the table in the TRM
// the max value represented for OSR 128 using sinc 3 is +/-2097152 i.e. 2^21
// to represent this in 16 bit format where the first bit is sign shift by 6 bits
SdfmRegs[i].DFPARM.bit.FEN = FILTER_ENABLE;
SdfmRegs[i].DFPARM.bit.SST = SINC3;
SdfmRegs[i].DFPARM.bit.DOSR = OSR_RATE;
//Configure Data filter data representation //
// Sdfm1RegsA.A[i].SDIPARM.bit.DR = DATA_16_BIT; //Data Representation (0/1 = 16/32b 2's complement)
SdfmRegs[i].IPARM.bit.SH = 6; //Shift control
//PWM11.CMPC, PWM11.CMPD, PWM12.CMPC and PWM12.CMPD signals cannot synchronize the filters. This option is not being used in this example.
SdfmRegs[i].DFPARM.bit.FILRESEN = 1; // im Datenblatt: SDSYNCEN
}
// Enable master filter bit of the SDFM module 1
SdfmRegs.MFILEN.bit.MFE = 1; //Master Filter bit is enabled
#ifdef CPU1
// ********************************************************************
//PWM 11 for syncing up the SD filter windows with motor control PWMs
// ********************************************************************
EPwm11Regs.CMPC = EPwm11Regs.TBPRD - SDFM_TICKS*(OSR_RATE+1)*3/2;
EPwm11Regs.CMPA.bit.CMPA = (SDFM_TICKS*(OSR_RATE+1)*3/2) + 500; // 500 is arbitrary
EPwm11Regs.CMPD = 0;
#endif
}
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