#pragma once
/**********
** GPIO **
**********/
// GpioDataRegs replacement / alias
struct GPIO_DATA_REGSAR {
struct GPIO_DATA_REGSA { // sizeof: 8
GPADAT_REG DAT;
GPASET_REG SET;
GPACLEAR_REG CLEAR;
GPATOGGLE_REG TOGGLE;
}A[6];
static void setbit(volatile uint32_t&v, uint8_t bitno) {v|=1UL<<bitno;}
bool getDAT (uint8_t io) volatile {return A[io>>5].DAT.all>>(io&31)&1;}
void setDAT(uint8_t io, bool v) volatile {if (v) doSET(io); else doCLEAR(io);}
void doSET (uint8_t io) volatile {setbit(A[io>>5].SET.all,io&31);}
void doCLEAR (uint8_t io) volatile {setbit(A[io>>5].CLEAR.all,io&31);}
void doTOGGLE(uint8_t io) volatile {setbit(A[io>>5].TOGGLE.all,io&31);}
volatile GPIO_DATA_REGSA&operator[](int i)volatile{return A[i];}
};
#define GpioDataRegsA (*(volatile GPIO_DATA_REGSAR*)&GpioDataRegs)
// GpioCtrlRegs replacement / alias
#define P(x) private: x; public:
struct GPIO_CTRL_REGSA { // sizeof: 128
GPACTRL_REG CTRL;
GPAQSEL1_REG QSEL[2];
GPAMUX1_REG MUX[2];
GPADIR_REG DIR;
GPAPUD_REG PUD;
P(Uint32 rsvd1)
GPAINV_REG INV;
GPAODR_REG ODR;
P(Uint32 rsvd2[6])
GPAGMUX1_REG GMUX[2];
P(Uint32 rsvd3[2])
GPACSEL1_REG CSEL[4];
P(Uint32 rsvd4[6])
GPALOCK_REG LOCK;
GPACR_REG CR;
static void orbits(volatile uint32_t&v, uint32_t bits, uint8_t shl) {v |= bits<<shl;}
void orQSEL(uint8_t io, uint8_t v) volatile {orbits(QSEL[io>>4].all,v,(io&15)<<1);}
void orMUX (uint8_t io, uint8_t v) volatile {orbits(GMUX[io>>4].all,v>>2,(io&15)<<1);orbits(MUX[io>>4].all,v&3,(io&15)<<1);}
void orDIR (uint8_t io) volatile {orbits(DIR.all,1,io);}
void orPUD (uint8_t io) volatile {orbits(PUD.all,1,io);}
void orINV (uint8_t io) volatile {orbits(INV.all,1,io);}
void orODR (uint8_t io) volatile {orbits(ODR.all,1,io);}
void orCSEL(uint8_t io, uint8_t v) volatile {orbits(CSEL[io>>3].all,v,(io&7)<<2);}
void orLOCK(uint8_t io) volatile {orbits(LOCK.all,1,io);}
void orBits(uint8_t,unsigned) volatile;
};
struct GPIO_CTRL_REGSAR {
GPIO_CTRL_REGSA A[6];
static void setbit(volatile uint32_t&v, uint8_t bitno, bool bit) {uint32_t m=1UL<<bitno; if (bit) v|=m; else v&=~m;}
static void setbits(volatile uint32_t&v, uint32_t mask, uint32_t bits) {v = v&~mask | bits;}
static void set2bits(volatile uint32_t&v, uint8_t bitno, uint8_t bits) {bitno<<=1; setbits(v,3UL<<bitno,(uint32_t)bits<<bitno);}
static void set4bits(volatile uint32_t&v, uint8_t bitno, uint8_t bits) {bitno<<=2; setbits(v,15UL<<bitno,(uint32_t)bits<<bitno);}
static void set8bits(volatile uint32_t&v, uint8_t bitno, uint8_t bits) {bitno<<=3; setbits(v,255UL<<bitno,(uint32_t)bits<<bitno);}
void setCTRL(uint8_t io, bool v) volatile {set8bits(A[io>>5].CTRL.all,io>>3&3,v);}
void setQSEL(uint8_t io, uint8_t v) volatile {set2bits(A[io>>5].QSEL[io>>4&1].all,io&15,v);}
void setMUX (uint8_t io, uint8_t v) volatile {set2bits(A[io>>5].GMUX[io>>4&1].all,io&15,v>>2);set2bits(A[io>>5].MUX[io>>4&1].all,io&15,v&3);}
void setDIR (uint8_t io, bool v) volatile {setbit(A[io>>5].DIR.all,io&31,v);}
void setPUD (uint8_t io, bool v) volatile {setbit(A[io>>5].PUD.all,io&31,v);}
void setINV (uint8_t io, bool v) volatile {setbit(A[io>>5].INV.all,io&31,v);}
void setODR (uint8_t io, bool v) volatile {setbit(A[io>>5].ODR.all,io&31,v);}
void setCSEL(uint8_t io, uint8_t v) volatile {set4bits(A[io>>5].CSEL[io>>3&3].all,io&7,v);}
void setLOCK(uint8_t io, bool v) volatile {setbit(A[io>>5].LOCK.all,io&31,v);}
void setCR (uint8_t io, bool v) volatile {setbit(A[io>>5].CR.all,io&31,v);}
volatile GPIO_CTRL_REGSA&operator[](int i) volatile {return A[i];}
};
#define GpioCtrlRegsA (*(volatile GPIO_CTRL_REGSAR*)&GpioCtrlRegs)
/**********
** SDFM **
**********/
// Handlichere SDFM-Register-Beschreibung (als in F2837xD.h)
// Muss binärkompatibel zu SDFM_REGS sein!!
struct SDFM_REGSA { // sizeof: 128
SDIFLG_REG IFLG;
SDIFLGCLR_REG IFLGCLR;
SDCTL_REG CTL;
P(Uint16 rsvd1)
SDMFILEN_REG MFILEN;
P(Uint16 rsvd2)
struct FM_CHANNEL{
P(Uint16 rsvd[8])
SDCTLPARM1_REG CTLPARM;
SDDFPARM1_REG DFPARM;
SDIPARM1_REG IPARM;
SDCMPH1_REG CMPH;
SDCMPL1_REG CMPL;
SDCPARM1_REG CPARM;
union{
SDDATA1_REG DATA;
int32_t I32;
uint32_t U32;
struct{int16_t IL16,IH16;};
struct{uint16_t UL16,UH16;};
};
}A[4]; // Für jeden der 4 Filter-Kanäle ein gleiches Array (mit Typen vom Kanal 1)
P(Uint16 rsvd6[56])
volatile FM_CHANNEL&operator[](int i) volatile {return A[i];}
};
#define Sdfm1RegsA (*(volatile SDFM_REGSA*)&Sdfm1Regs)
#define Sdfm2RegsA (*(volatile SDFM_REGSA*)&Sdfm2Regs)
#define SdfmRegsA ((volatile SDFM_REGSA*)&Sdfm1Regs)
/*********
** ADC **
*********/
struct ADC_REGSA { // sizeof: 0x80
ADCCTL1_REG CTL1; // @ 0x00
ADCCTL2_REG CTL2;
ADCBURSTCTL_REG BURSTCTL;
ADCINTFLG_REG INTFLG;
ADCINTFLGCLR_REG INTFLGCLR;
ADCINTOVF_REG INTOVF;
ADCINTOVFCLR_REG INTOVFCLR;
ADCINTSEL1N2_REG INTSEL[2];
ADCSOCPRICTL_REG SOCPRICTL;
ADCINTSOCSEL1_REG INTSOCSEL[2];
ADCSOCFLG1_REG SOCFLG1;
ADCSOCFRC1_REG SOCFRC1;
ADCSOCOVF1_REG SOCOVF1;
ADCSOCOVFCLR1_REG SOCOVFCLR1;
ADCSOC0CTL_REG SOCCTL[16]; // 32 @0x10
ADCEVTSTAT_REG EVTSTAT; // @ 0x30
P(Uint16 rsvd1)
ADCEVTCLR_REG EVTCLR;
P(Uint16 rsvd2)
ADCEVTSEL_REG EVTSEL;
P(Uint16 rsvd3)
ADCEVTINTSEL_REG EVTINTSEL;
P(Uint16 rsvd4[2])
ADCCOUNTER_REG COUNTER;
ADCREV_REG REV;
ADCOFFTRIM_REG ADCOFFTRIM;
int16_t rsvd5[4];
struct{ // @ 0x40 size=8
ADCPPB1CONFIG_REG CONFIG;
ADCPPB1STAMP_REG STAMP;
ADCPPB1OFFCAL_REG OFFCAL;
Uint16 OFFREF;
ADCPPB1TRIPHI_REG TRIPHI; // 32
ADCPPB1TRIPLO_REG TRIPLO; // 32
}PPB[4];
Uint32 rsvd6[8]; // @ 0x60
Uint32 INLTRIM[6]; // @ 0x70
Uint32 rsvd7[2];
};
#define AdcaRegsA (*(volatile ADC_REGSA*)&AdcaRegs)
#define AdcbRegsA (*(volatile ADC_REGSA*)&AdcbRegs)
#define AdccRegsA (*(volatile ADC_REGSA*)&AdccRegs)
#define AdcdRegsA (*(volatile ADC_REGSA*)&AdcdRegs)
#define AdcRegsA ((volatile ADC_REGSA*)&AdcaRegs)
struct ADC_RESULT_REGSA { // sizeof: 0x20
Uint16 RESULT[16];
ADCPPB1RESULT_REG ADCPPB[4]; // @ 0x10
P(Uint32 rsvd1[4])
volatile Uint16&operator[](int i) volatile {return RESULT[i];}
};
#define AdcaResultRegsA (*(volatile ADC_RESULT_REGSA*)&AdcaResultRegs)
#define AdcbResultRegsA (*(volatile ADC_RESULT_REGSA*)&AdcbResultRegs)
#define AdccResultRegsA (*(volatile ADC_RESULT_REGSA*)&AdccResultRegs)
#define AdcdResultRegsA (*(volatile ADC_RESULT_REGSA*)&AdcdResultRegs)
#define AdcResultRegsA ((volatile ADC_RESULT_REGSA*)&AdcaResultRegs)
struct ANALOG_SUBSYS_REGSA {
P(Uint16 rsvd1[32])
INTOSC1TRIM_REG INTOSCTRIM[2];
P(Uint16 rsvd2[2])
TSNSCTL_REG TSNSCTL;
P(Uint16 rsvd3[7])
LOCK_REG LOCK;
P(Uint16 rsvd4[6])
ANAREFTRIMA_REG ANAREFTRIM[4];
P(Uint16 rsvd5[10])
};
#define AnalogSubsysRegsA (*(volatile ANALOG_SUBSYS_REGSA*)&AnalogSubsysRegs)
/*********
** PIE **
*********/
struct PIE_CTRL_REGSA {
PIECTRL_REG PIECTRL;
PIEACK_REG PIEACK;
struct GROUP{
PIEIER1_REG PIEIER;
PIEIFR1_REG PIEIFR;
}A[12];
volatile GROUP&operator[](int i) volatile {return A[i];}
};
#define PieCtrlRegsA (*(volatile PIE_CTRL_REGSA*)&PieCtrlRegs)
#undef P
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