/* Projekt: maweig-Motor mit Delfino-Launchpad
Teil: Systeminitialisierung
191004 erstellt
*/
#include "Settings.h"
#include "regdef2.h"
/***************************************************
** modifizierte Kopien aus F2837xD_xxx.c-Dateien **
***************************************************/
// must have EALLOW environment
RAMFUNC static void initFlash() {
//At reset bank and pump are in sleep
//A Flash access will power up the bank and pump automatically
//After a Flash access, bank and pump go to low power mode (configurable in FBFALLBACK/FPAC1 registers)-
//if there is no further access to flash
//Power up Flash bank and pump and this also sets the fall back mode of flash and pump as active
Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1;
Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3;
//Cache and prefetch mechanism must be clear before changing wait states
//Minimum waitstates found in sprs880k.pdf:69
Flash0CtrlRegs.FRDCNTL.all =
F_CPU > 150E6 ? 3<<8 :
F_CPU > 100E6 ? 2<<8 :
F_CPU > 50E6 ? 1<<8 : 0;
//Enable Cache and prefetch mechanism
Flash0CtrlRegs.FRD_INTF_CTRL.all = 3;
//Force a pipeline flush before returning.
__asm(" RPT #7 || NOP");
}
// must have EALLOW environment
static void serviceDog() {
WdRegs.WDKEY.bit.WDKEY = 0x0055;
WdRegs.WDKEY.bit.WDKEY = 0x00AA;
}
// must have EALLOW environment
static void disableDog() {
WdRegs.WDCR.all = 0x0068 | WdRegs.WDCR.all & 0x0007;
}
// must have EALLOW environment
static void initSysPll() {
ClkCfgRegs.CLKSRCCTL1.all = 1; // Taktquelle: Quarz 10 MHz
// Program PLL multipliers
ClkCfgRegs.SYSPLLMULT.all = 20; // 20-fach
ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1; // Enable SYSPLL
// Wait for the SYSPLL lock
while (!ClkCfgRegs.SYSPLLSTS.bit.LOCKS) serviceDog();
// Write a multiplier again to ensure proper PLL initialization
// This will force the PLL to lock a second time
ClkCfgRegs.SYSPLLMULT.all = 20;
// Wait for the SYSPLL re-lock
while (!ClkCfgRegs.SYSPLLSTS.bit.LOCKS) serviceDog();
// Enable PLLSYSCLK is fed from system PLL clock
ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; // now feed the CPU
// Small 100 cycle delay
asm(" RPT #100 || NOP");
// Set the divider (/4 at reset) to maximum speed
ClkCfgRegs.SYSCLKDIVSEL.all = 0;
}
static void initSysCtrl() {
// Disable the watchdog (1. Passiert das nicht schon früher einmal?? 2. Scheiße!)
disableDog();
initFlash();
// *IMPORTANT*
// The Device_cal function, which copies the ADC & oscillator calibration values
// from TI reserved OTP into the appropriate trim registers, occurs automatically
// in the Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC and oscillators to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference Manual for more information.
#ifdef CPU1
//enable all pull-ups to reduce power consumption
for (int i=0; i<6; i++) GpioCtrlRegsA[i].PUD.all=0;
PCLKCR13_REG o={CpuSysRegs.PCLKCR13.all}, n={0};
n.bit.ADC_A = 1;
n.bit.ADC_B = 1;
n.bit.ADC_C = 1;
n.bit.ADC_D = 1;
CpuSysRegs.PCLKCR13.all = n.all;
//check if device is trimmed
if(!*((Uint16 *)0x5D1B6)) for (int i=0; i<4; i++) {
//device is not trimmed, apply static calibration values
AnalogSubsysRegsA.ANAREFTRIM[i].all = 31709;
}
CpuSysRegs.PCLKCR13.all = o.all;
initSysPll(); // Initialize the PLL control: PLLCR and CLKINDIV
#endif
//Turn on all peripherals (Scheiße!)
// CpuSysRegs.PCLKCR0.bit.CLA1 = 1;
// CpuSysRegs.PCLKCR0.bit.DMA = 1;
CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1;
CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1;
// CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1;
#ifdef CPU1
// CpuSysRegs.PCLKCR0.bit.HRPWM = 1;
#endif
// CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
{ PCLKCR2_REG reg = {0};
#ifdef CPU1
reg.bit.EPWM1 = 1;
reg.bit.EPWM2 = 1;
reg.bit.EPWM3 = 1;
// reg.bit.EPWM7 = 1;
reg.bit.EPWM8 = 1;
reg.bit.EPWM9 = 1;
// reg.bit.EPWM10 = 1;
reg.bit.EPWM11 = 1;
// reg.bit.EPWM12 = 1;
#endif
#ifdef CPU2
reg.bit.EPWM4 = 1;
reg.bit.EPWM5 = 1;
reg.bit.EPWM6 = 1;
#endif
CpuSysRegs.PCLKCR2.all = reg.all;
}
// CpuSysRegs.PCLKCR3.bit.ECAP1 = 1;
// CpuSysRegs.PCLKCR3.bit.ECAP2 = 1;
// CpuSysRegs.PCLKCR3.bit.ECAP3 = 1;
// CpuSysRegs.PCLKCR3.bit.ECAP4 = 1;
// CpuSysRegs.PCLKCR3.bit.ECAP5 = 1;
// CpuSysRegs.PCLKCR3.bit.ECAP6 = 1;
CpuSysRegs.PCLKCR4.bit.EQEP1 = 1;
CpuSysRegs.PCLKCR4.bit.EQEP2 = 1;
// CpuSysRegs.PCLKCR4.bit.EQEP3 = 1;
CpuSysRegs.PCLKCR6.bit.SD1 = 1;
CpuSysRegs.PCLKCR6.bit.SD2 = 1;
CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
CpuSysRegs.PCLKCR7.bit.SCI_B = 1;
CpuSysRegs.PCLKCR7.bit.SCI_C = 1;
// CpuSysRegs.PCLKCR7.bit.SCI_D = 1;
CpuSysRegs.PCLKCR8.bit.SPI_A = 1;
CpuSysRegs.PCLKCR8.bit.SPI_B = 1;
// CpuSysRegs.PCLKCR8.bit.SPI_C = 1;
// CpuSysRegs.PCLKCR9.bit.I2C_A = 1;
// CpuSysRegs.PCLKCR9.bit.I2C_B = 1;
// CpuSysRegs.PCLKCR10.bit.CAN_A = 1;
// CpuSysRegs.PCLKCR10.bit.CAN_B = 1;
// CpuSysRegs.PCLKCR11.bit.McBSP_A = 1;
// CpuSysRegs.PCLKCR11.bit.McBSP_B = 1;
#ifdef CPU1
// CpuSysRegs.PCLKCR11.bit.USB_A = 1;
// CpuSysRegs.PCLKCR12.bit.uPP_A = 1;
#endif
{ PCLKCR13_REG reg = {0};
reg.bit.ADC_A = 1;
reg.bit.ADC_B = 1;
reg.bit.ADC_C = 1;
// reg.bit.ADC_D = 1;
CpuSysRegs.PCLKCR13.all = reg.all;
}
{ PCLKCR14_REG reg = {0};
reg.bit.CMPSS1 = 1;
reg.bit.CMPSS2 = 1;
reg.bit.CMPSS3 = 1;
reg.bit.CMPSS4 = 1;
reg.bit.CMPSS5 = 1;
reg.bit.CMPSS6 = 1;
reg.bit.CMPSS7 = 1;
reg.bit.CMPSS8 = 1;
CpuSysRegs.PCLKCR14.all = reg.all;
}
CpuSysRegs.PCLKCR16.bit.DAC_A = 1;
CpuSysRegs.PCLKCR16.bit.DAC_B = 1;
CpuSysRegs.PCLKCR16.bit.DAC_C = 1;
}
static void initPieCtrl() {
// Disable Interrupts at the CPU level:
DINT;
// Disable the PIE
PieCtrlRegsA.PIECTRL.bit.ENPIE = 0;
for (int i=0; i<12; i++) PieCtrlRegsA[i].PIEIER.all = 0;
for (int i=0; i<12; i++) PieCtrlRegsA[i].PIEIFR.all = 0;
}
static interrupt void dummyISR() {
asm (" ESTOP0");
for(;;);
}
// Kopie von InitPieVectTable, aber mit nur _einer_ Dummy-ISR
static void initPieVectTable() {
PINT*Dest = ((PINT*)&PieVectTable)+3;
// Do not write over first 3 32-bit locations (these locations are
// initialized by Boot ROM with boot variables)
for (int i=3; i<224; i++) *Dest++ = dummyISR;
// Enable the PIE Vector Table
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
}
void SysInit::InitAll() {
#ifdef _FLASH
// Copy time critical code and Flash setup code to RAM
// The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
// symbols are created by the linker. Refer to the linker files.
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (Uint32)&RamfuncsLoadSize);
#endif
EALLOW;
#ifdef CPU1 // muss vorher geschehen!
CPUSEL0_REG cpusel0 = {0};
cpusel0.bit.EPWM6 = cpusel0.bit.EPWM5 = cpusel0.bit.EPWM4 = 1;
DevCfgRegs.CPUSEL0.all = cpusel0.all;
DevCfgRegs.CPUSEL2.bit.EQEP2 = 1;
DevCfgRegs.CPUSEL4.bit.SD2 = 1;
DevCfgRegs.CPUSEL5.bit.SCI_C = 1;
#endif
// PLL, WatchDog, all(!) Peripheral Clocks
// This example function is found in the F28M3Xx_SysCtrl.c file.
initSysCtrl();
// 2. ruft InitFlash()
//IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);
ClkCfgRegs.LOSPCP.all = F_CPU/F_LSP-0.1; // LSPCLK = 200 MHz (für SPI)
// GpioDataRegs.GPASET.all = bit(31); // GPIO31 auf High — Blaue LED aus
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F28M3Xx_PieCtrl.c file.
initPieCtrl();
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table.
// The shell ISR routines are found in F28M3Xx_DefaultIsr.c.
// This function is found in F28M3Xx_PieVect.c.
initPieVectTable();
}
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