Application Notes for HD61830

1. Introduction

The HD61830(B) graphics controller chip is designed to control small to medium size graphic Liquid Crystal Display modules (LCD). It may be interfaced with a number of different 8-bit micro-processor units (MPU). It provides the necessary interface between the MPU and the video RAM (VRAM), sometimes referred to as Display RAM or Refresh RAM. It also generates the necessary timing and data signals for the liquid crystal driver circuits. It has a built-in 192 character Character-Generator ROM (CG-ROM) and Character Generator (CG) circuits. The HD61830(B) has the capability to control upto 64K bytes of external display RAM in graphics mode and 4K bytes in the character mode. Most designs using the HD61830(B) only implement 2K to 8K of VRAM depending on the size of LCD screen. This VRAM may be allocated for text or graphics. The HD61830(B) can support a wide variety of LCD formats.

This application note is Written with any specific display in mind but is intended to give a thorough understanding of how to use the HD61830(B) and implement the software/hardware interface. Some LCD modules will have the HD61830(B) controller built into the module such as the LM31XX and LM41XX series of LCD modules, others require an external graphics controller. This application note is applicable to the LM1001GC, LM1002GC and LM1006GC graphics controller cards available from Densitron as well as to Densitron LCD modules with on-board HD61830(B) graphics controllers.


2. Main Functions and Features of the HD61830

  • Simple 8-bit parallel Interface
  • Built in Character Generator and font table (160, 5x7 plus 32, 5x11 characters)
  • External CG-ROM option for upto 256 character font table
  • Software Selectable Cursor ON/OFF/BLINK attributes
  • Software instructions for scrolling, character blink and bit manipulation
  • Software Selectable Character or Graphics modes
  • Software selectable Duty (1 to 1/128)
  • Software Selectable Character Cell size (6x8 upto 8x16)
  • Low power CMOS design
Note: Not all these features are implemented on Densitron LCD modules or LM100X series controller cards.


3. Electrical Specifications for HD61830/HD61830B

3.1 Absolute Maximum Ratings

Item | Symbol | Value | Units
Power supply voltage | UCC | -0.3 to 7.0 | V
Input voltage | Uin | -0.3 to UCC+0.3 | V
Operating Temperature | Top | -20 to 75 | °C
Storage Temperature | Tstg | -55 to 125 | °C

Notes:

  1. All voltages are referenced to GND=0V
  2. Specification is for HD61830(B) only. LCD module specifications may differ.

3.2 Electrical Characteristics

(UCC=+5V±10%, GND=0V, Ta=-20 to +75°C)

Item |  | Symbol | Condition | Min | Max | Units | Notes
Input voltage | "H" | UIH |  | 2.2 | UCC | V | 1, 4
(TTL Level) | "L" | UIL |  | 0 | 0.8 | V | 1, 2, 4
 | "H" | UIHR |  | 3.0 | UCC | V | 2
Input voltage | "H" | UIHC |  | 0.7UCC | UCC | V | 3, 7
(CMOS Level) | "L" | UILC |  | 0 | 0.3UCC | V | 3, 7
Output voltage | "H" | UOH | -IOH=0.6mA | 2.4 | UCC | V | 4
(TTL level) | "L" | UOL | IOL=1.6mA | 0 | 0.4 | V | 4
Output voltage | "H" | UOHC | -IOH=0.6mA | UCC-0.4 | UCC | V | 5, 6
(CMOS level) | "L" | UOLC | IOL=0.6mA | 0 | 0.4 | V | 5, 6
Input leakage current |  | IIL | Uin=0~UCC | -5 | 5 | µA | 4
Output leakage current |  | IOL | Uout=0~UCC | -10 | 10 | µA | 4
Internal Oscillation |  | fosc | Cf=15p±5% Rf=39K±2% fosc=500KHz | 400 | 600 | KHz | 3
External clock frequency |  | fcp |  | 100 100 | 1100 2400 | KHz | 3, 7
External clock Duty |  | Duty |  | 47.5 | 52.5 | % | 3, 7
Ext. clock rise/fall time |  | trcp, tfcp |  | - | 50 25 | ns | 3 7

Notes:

  1. E, CS, RS, R/W
  2. RST
  3. CR for HD61830
  4. DB0 to DB7
  5. FLM, CL1, CL2
  6. D1, D2, M
  7. CR for HD61830B


4. Interface Pin Connections

4.1 MPU Interface Pin Functions

Pin-outs differ for individual LCD modules with on-board controllers. Please refer to individual module data sheets for pin assignment information.

Pin Name | I/O | Pin Function
USS | - | Ground
UCC | - | Logic Supply (+5V)
RS | I | Register Select: "1" = Instruction Register "0" = Data Register
R/W | I | Read/Write: "1" = Read from HD61830(B) "0" = Write to HD61830(B)
E | I | Enable (Active High)
DB0 | I/O | Bi-directional Data Bus Line 0
DB1 | I/O | Bi-directional Data Bus Line 1
DB2 | I/O | Bi-directional Data Bus Line 2
DB3 | I/O | Bi-directional Data Bus Line 3
DB4 | I/O | Bi-directional Data Bus Line 4
DB5 | I/O | Bi-directional Data Bus Line 5
DB6 | I/O | Bi-directional Data Bus Line 6
DB7 | I/O | Bi-directional Data Bus Line 7
CS | I | Chip Select (Active Low)
RST | I | Reset (Active Low)

4.2 LCD Interface Pin Functions

For LCD modules with on-board controllers, these signals are not generally accessible. However for the LM1001GC, LM1002GC and LM1006GC graphics controller cards these signals are available; refer to individual data sheets for pin assignments.

Pin Name | I/O | Pin Function
D1 | O | Serial Data Line 1
FLM | O | First Line Marker (Start of Frame)
M | O | Control Signal for AC drive of LC
CL1 | O | Latch clock
CL2 | O | Shift clock for serial data
D2 | O | Serial Data Line 2
UDD | - | Power supply for logic circuits
USS | - | Ground
UEE | - | Power supply for LC drivers
UO | - | Operating voltage for LC drivers (Contrast)


5. Timing Characteristics

5.1 MPU Interface Timing (MPU - HD61830)

Item |  | Symbol | Min | Typ | Max | Unit
Enable cycle time |  | tCYC | 1.0 | - | - | µs
Enable pulse width | "H" | tWEH | 0.45 | - | - | µs
 | "L" | tWEL | 0.45 | - | - | µs
Enable rise time |  | tEr | - | - | 25 | ns
Enable fall time |  | tEf | - | - | 25 | ns
Set up time |  | tAS | 140 | - | - | ns
Data set up time |  | tDSW | 225 | - | - | ns
Data delay time |  | tDDR | - | - | 225 | ns
Data hold time (Write) |  | tDHW | 10 | - | - | ns
Address hold time |  | tAH | 10 | - | - | ns
Data Hold Time (Read) |  | tDH | 20 | - | - | ns
Pulse width of /RES |  | tWRES | 1µs | - | 2ms | -

Note: MPU interface timing for HD61830B is identical to HD61830

Figure 5.1: MPU Interface Timing (MPU - HD61830(B))

5.2 LCD Interface Timing (HD61830 - LCD)

Item |  | Symbol | Min | Typ | Max | Unit
Clock pulse width (high level) |  | tWCL1 | 450 | - | - | ns
Clock delay time |  | tDCL2 | - | - | 200 | ns
Clock cycle time |  | tWCL2 | 900 | - | - | ns
Clock pulse width | "H" | tWCH | 450 | - | - | ns
 | "L" | tWCL | 450 | - | - | ns
M delay time |  | tMD | - | - | 300 | ns
FLM delay time |  | tDF | - | - | 300 | ns
Data delay time |  | tDD | - | - | 200 | ns
Data set up time |  | tSD | 250 | - | - | ns

Note: No load is applied to all outputs.

Figure 5.2: LCD Interface Timing (HD61830 - LCD)

5.3 LCD Interface Timing (HD61830B - LCD)

Item |  | Symbol | Min | Typ | Max | Unit | Note
Clock cycle time |  | tWCL2 | 416 | - | - | ns | 1
Clock pulse width | "H" | tWCH | 150 | - | - | ns | 1
 | "L" | tWCL | 150 | - | - | ns | 1
Data delay time |  | tDD | - | - | 50 | ns | 1
Data hold time |  | tDH | 100 | - | - | ns | 1
M delay time |  | tDM | -200 | - | 200 | ns | 1
FLM set up time |  | tSF | 400 | - | - | ns | 2
FLM hold time |  | tHF | 1000 | - | - | ns | 2
M set up time |  | tSMA | 400 | - | - | ns | 2
M hold time |  | tHMA | 1000 | - | - | ns | 2

Note 1 -

Note 2 -

Figure 5.3: LCD Interface Timing (HD61830B - LCD)


6. System Block Diagram

All liquid crystal displays require two power sources UCC for logic circuits and UEE for Liquid Crystal (LC) drive. Some graphics LCD modules will run directly of a single UCC supply by generating the UEE voltage on-board; others will require an external DC-DC converter to generate the negative UEE voltage. Refer to individual specifications for details.

Figure 6.1: System Block Diagram


7. Power Supply Sequencing and RST Terminal

To prevent latch-up of the CMOS LSI (HD61830(B) and LCD driver LSI) ensure your systems power supply follows the following sequence. The UDD must be applied with a small time delay befor UEE is turned on. It is very important to follow this sequence in order to prevent the CMOS LSI from latching up and to prevent DC signals from being applied to the LC material. If the UEE voltage is applied before the timing signals M, CL1, CL2, and FLM then a DC voltage will be applied to the LC material. Over time this will degrade the LC fluid performance due to their electro-chemical behavior. If this power-up sequence is not adhered to, permanent damage to the LCD module may result.

Figure 7.1: Power Supply Sequence

The RESET circuit shown in Figure 7.2 is recommended to correctly reset the HD61830(B). On RESET the internal registers of the HD61830(B) are cleared and the BUSY flag is reset, Display is turned off, HP=6 and HD61830 is set for Slave mode (Refer to section 8 for detail).

Figure 7.2: RESET Circuit


8. HD61830(B) Instruction Set

The following is a summary of available instructions for use with the HD61830(B).

Table 8.0: HD61830(B) Instruction Set

R/W | RS | DB7 MSB | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DB0 LSB | Function
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Set Mode Control Register
0 | 0 | 0 | 0 | Mode Control data |  |  |  |  |  | Mode Control data
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Set Character Pitch Register
0 | 0 | (VP-1) binary |  |  |  | 0 | (HP-1) binary |  |  | Vertical/Horizontal Pitch data
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Set Horizontal Count Register
0 | 0 | 0 | (HN-1) binary |  |  |  |  |  |  | Horizontal Count data
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | Set Multiplex Ratio Register
0 | 0 | 0 | (NX-1) binary |  |  |  |  |  |  | Multiplex ratio data (1/Duty-1)
 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Set Cursor Position Register
0 | 0 | 0 | 0 | 0 | 0 | (CP-1) binary |  |  |  | Cursor Position data
0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Set Lower Dis. Start Addr Reg
0 | 0 | (Low order Display Start Address) binary |  |  |  |  |  |  |  | Lower Display Start Addr. data
0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | Set Upper Display Start Addr Reg
0 | 0 | (High order Display Start Address) binary |  |  |  |  |  |  |  | Upper Display Start Address data
0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | Set Lower Cursor Addr Reg
0 | 0 | (Low order Cursor Address) binary |  |  |  |  |  |  |  | Lower Cursor Address data
0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | Set Upper Cursor Addr Reg
0 | 0 | (High order Cursor Address) binary |  |  |  |  |  |  |  | Upper Cursor Address data
0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | Write-VRAM Instruction
0 | 0 | MSB (Character code or bit-map data) LSB |  |  |  |  |  |  |  | Display data
0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | Read-VRAM Instruction
1 | 0 | MSB (Character code or bit-map data) LSB |  |  |  |  |  |  |  | Display data
0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | Bit Clear Instruction
0 | 0 | 0 | 0 | 0 | 0 | 0 | (NB-1) binary |  |  | Bit Address
0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | Bit Set Instruction
0 | 0 | 0 | 0 | 0 | 0 | 0 | (NB-1) binary |  |  | Bit Address
1 | 1 | BF | * | * | * | * | * | * | * | Read BUSY FLAG

Notes:

  1. * = DON'T CARE
  2. Read the status of the Busy Flag before each new instruction is sent to the HD61830(B). If the HD61830(B) Busy Flag is set (BF=1) then the HD61830(B) is busy processing the previous instruction. If a new instruction is sent to the HD61830(B) while the Busy Flag, BF=1, then that command shall be ignored by the HD61830(B).
  3. Vertical Character Pitch, VP:0 < (VP-1) < 15
  4. Horizontal Character Pitch,HP:5 < (HP-1) < 7
  5. Horizontal Character Count, HN:HN < 128, HN must be an even integer.
  6. Multiplex Ratio, NX: NX=1/Duty, NX < 128

8.1 Mode Control Register

R/W | RS | DB7 | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DB0 | Function
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Set Mode Control Register
0 | 0 | 0 | 0 | D5 | D4 | D3 | D2 | D1 | D0 | Mode Control data
 |  |  |  | | | | | | | | | | | 0 | HD61830(B) Internal CG ROM
 |  |  |  | | | | | | | | | | | 1 | External CG ROM
 |  |  |  | | | | | | | | | 0 | -- | Character mode
 |  |  |  | | | | | | | | | 1 | -- | Graphics mode
 |  |  |  | | | | | 0 | 0 | -- | -- | Cursor OFF
 |  |  |  | | | | | 0 | 1 | -- | -- | Cursor ON
 |  |  |  | | | | | 1 | 0 | -- | -- | Cursor OFF Character Blink
 |  |  |  | | | | | 1 | 1 | -- | -- | Cursor blank
 |  |  |  | | | 0 | -- | -- | -- | -- | Slave Mode
 |  |  |  | | | 1 | -- | -- | -- | -- | Master Mode
 |  |  |  | 0 | -- | -- | -- | -- | -- | Display OFF
 |  |  |  | 1 | -- | -- | -- | -- | -- | Display ON

The Mode Control register sets the operating mode for the HD61830(B). It controls the character/graphics mode, cursor, on/off/blink, master/slave and display on/off. When D1 is set to 1 and D0, D2 and D3 are set to 0, the HD61830(B) is set to graphics mode and the character generator and cursor functions are disabled.

Most displays and controller cards use only one HD61830 so D4=1. The LM1006GC is the exception as two HD61830 are used; one configured as the slave (D4=0) and the other as the master (D4=1).

8.2 Character Pitch Register

R/W | RS | DB7 | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DB0 | Function
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Set Character Pitch Register
0 | 0 | (VP-1) binary |  |  |  | 0 | (HP-1) binary |  |  | Vertical/Horizontal Pitch data

Character Mode: VP and HP set the horizontal and vertical size of each character cell. To display the 5x11 font stored in the CG-ROM set VP = 12 and HP=6. That is set the Character Pitch register to B5H. If displaying only the 5x7 font then set VP=8 and HP=6. That is set the Character Pitch register to 75H. A value in the range of 1 to 16 may be used for VP. A value in the range of 6 to 8 may be used for HP. Refer to section 9.0 for pictorial definitions of VP and HP.

Graphics Mode: VP has no meaning in Graphics mode and may be set to any value. HP should be set to 8. That is set Character Pitch register to 07H for Graphics mode.

8.3 Horizontal Count Register

R/W | RS | DB7 | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DB0 | Function
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Set Horizontal Count Instruction
0 | 0 | 0 | (HN-1) binary |  |  |  |  |  |  | Horizontal Count data

Character Mode: This register sets the number of horizontal characters that can be displayed on the LCD. The character width is defined by HP in the Character Pitch Register (Section 8.2).

Graphics Mode: This register sets the number of horizontal bytes that can be displayed on the LCD. For graphics mode, it is best to set HP=8.

If the total number of horizontal dots on the LCD screen is n then:

HN = n/HP

Note: HN must be an even integer value in the range 2 ≤ HN ≤ 128

For example: If using HD61830(B) to control a 64x240 LCD screen in Character Mode, with HP = 6 then set HN = 0x28. That is, write 27H into Horizontal Count register.

8.4 Multiplex Ratio Register (1/Duty)

R/W | RS | DB7 | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DB0 | Function
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | Set Multiplex Ratio Register
0 | 0 | 0 | (NX-1) binary |  |  |  |  |  |  | Multiplex ratio data [(1/Duty)-1]

Set NX to the Duty cycle ratio of the LCD being used. NX should be in the range 1 < NX < 128.

For example: For a 1/64 duty LCD screen set NX=64 and write 0x3F into Multiplex Ratio register.

8.5 Cursor Position Register

R/W | RS | DB7 | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DB0 | Function
0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Set Cursor Position Register
0 | 0 | 0 | 0 | 0 | 0 | (CP-1) binary |  |  |  | Cursor Position data

In Character Mode, CP indicates the position of the cursor within the character cell defined by VP and HP in the Character Pitch register (Section 8.2). The horizontal width of the cursor is equal to HP. A value of 1 to 16 may be set for CP. If CP > VP no cursor will be displayed. If CP ≤ VP the cursor has higher priority and the cursor shall be written over the top of the character on the LCD screen. CP = 1 means cursor will appear on top row of character cell; if CP = VP then cursor will appear on bottom row of character cell.

For example: To display a cursor underneath a 5x7 character, set CP = 8. That is write 0x07 into Cursor Position register. To display a cursor underneath a 5x11 character, set CP = 12. That is write 0x0B into Cursor Position register.

8.6 Display Start Address Registers

R/W | RS | DB7 | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DB0 | Function
0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Set Lower Display Start Addr Reg
0 | 0 | (Low order Display Start Address) binary |  |  |  |  |  |  |  | Lower Display start Addr. data
0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | Set Upper Display Start Addr Reg
0 | 0 | (High order Display Start Address) binary |  |  |  |  |  |  |  | Upper Display Start Addr. data

The High and Low order Display Start Address indicates a VRAM address at which the data displayed at the top left corner of the LCD screen is stored.

Character Mode: Set DB7~DB4 = 0, for High order Display Start Address. Only DB3~DB0 is valid for High order Display Start Address in the Character Mode. That is a value in the range of 0x0000 to 0x0FFF may be written into the High/Low order Display Start Address registers for the HD61830(B) Character Mode.

Graphics Mode: All 16 bits of the High/Low order Display Start Address register are valid for the Graphics Mode of the HD61830(B). A value in the range 0x0000 to 0xFFFF may be written into the High/Low order Display Start Address registers. However bear in mind that not all LCD modules or controller cards have this much addressable RAM on-board. Refer to individual LCD module specifications for size of addressable VRAM.

The Display Start Address registers are very useful when implementing scrolling both horizontally and vertically. The Display Start Address may be incremented or decremented by the value HN (section 8.3) to scroll up or down by one row of dots in the Graphics mode or by one character row (set by VP) in the Character mode. By incrementing/decrementing the Display Start Address by one will cause the LCD screen to shift horizontally left/right by the number of dots set by the value HP (section 8.2) as shown below.

For Example:

A | B | C | -- | -- | -- | D |  |  | A | B | C | -- | -- | -- | D | E |
E | F | G |  |  |  | H |  |  |  | F | G |  |  |  | H | I |
I | | |  |  |  |  | | |  |  |  |  | | |  |  |  |  | | |
 | | |  |  |  |  | | |  |  |  |  | | |  |  |  |  | | |
 | | |  |  |  |  | | |  |  |  |  | | |  |  |  |  | | |
 |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  | J |
J | K | L | -- | -- | -- | M |  |  |  | K | L | -- | -- | -- | M | N |
N | O | P | -- | -- | -- | Q | R | S |  | O | P | -- | -- | -- | Q | R | S

Before Incrementing Display Start Address.... After Incrementing Display Start Address....

8.7 Cursor Address Register (VRAM write address register)

R/W | RS | DB7 | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DB0 | Function
0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | Set Lower Cursor Addr Reg
0 | 0 | (Low order Cursor Address) binary |  |  |  |  |  |  |  | Lower Cursor Address data
0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | Set Upper Cursor Addr Reg
0 | 0 | (High order Cursor Address) binary |  |  |  |  |  |  |  | Upper Cursor Address data

The Cursor Address registers set the address for reading/writing display data to the VRAM. Always write to the Low Order Cursor Address register first followed by the High order Cursor Address register. The High order Cursor Address register may be updated independently from the Low order Cursor Address register; however if the Low order Cursor Address register is updated then the High order Cursor Address register must also be updated directly afterwards.

The Cursor Address is automatically incremented by +1 after each successive Write-VRAM, Read-VRAM, Bit Set or Bit Clear instruction.

Character Mode: Set DB7~DB4 = 0, for High order Cursor Address. Only DB3~DB0 is valid for High order Cursor Address in the Character Mode. That is a value in the range of 0x0000 to 0x0FFF may be written into the High/Low order Display Start Address registers for the HD61830(B) Character Mode.

Graphics Mode: All 16 bits of the High/Low order Cursor Address register are valid for the Graphics Mode of the HD61830(B). A value in the range 0x0000 to 0xFFFF may be written into the High/Low order Cursor Address registers. However bear in mind that not all LCD modules have this much addressable RAM on-board. Refer to individual LCD module specifications for size of addressable VRAM.

8.8 Write Data to VRAM Instruction

R/W | RS | DB7 | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DB0 | Function
0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | Write-VRAM Instruction
0 | 0 | MSB (Character code or bit-map data) LSB |  |  |  |  |  |  |  | Display data

Character Mode: This instruction will load the character code data into VRAM at the address specified by the current value stored in the Cursor Address register (section 8.7). The Cursor Address register will increment by +1 after each successive Write-VRAM instruction. Therefore to write DENSITRON to VRAM address 0x01FF, write the following sequence of commands to the HD61830(B):

STEP # | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14
DB7~DB0 | 0A | FF | 0B | 01 | 0C | 44 | 45 | 4E | 53 | 49 | 54 | 52 | 4F | 4E
RS | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
R/W | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0

Note: Check Busy Flag (BF) before steps 1, 3, and 5. All values are hexadecimal.

In order to move the word DENSITRON so that it is visible at the top left hand corner of the LCD screen set the Display Start Address register to 0x01FF (section 8.6). Note that if the character code written to VRAM is not recognized by the CG-ROM then a blank character will be displayed on the LCD screen (Refer to section 14.0).

Graphics Mode: This instruction will load a byte of data into VRAM at the address specified by the current value stored in the Cursor Address (section 8.7). The Cursor Address register will increment by +1 after each successive Write-Vram instruction. The least significant bit (LSB) of each byte written to VRAM correspondes to the left most dot on the LCD screen (See section 10.0)

8.9 Read data from VRAM Instruction

R/W | RS | DB7 | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DB0 | Function
0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | Read-VRAM Instruction
1 | 0 | MSB (Character code or bit-map data) LSB |  |  |  |  |  |  |  | Display data

This instruction outputs the data stored in the VRAM at the address immediately preceding the current Cursor Address. The Cursor Address is incremented by +1 after each successive Read-VRAM instruction. To read the VRAM data at the current Cursor Address it will be necessary to do a dummy Read-VRAM instruction so that the Cursor address is incremented by +1 before issuing the next read instruction which will put valid data on the data bus. For example assume DENSITRON is stored in VRAM starting at address 0x01FF. The following sequence will read the data stored at addresses 0x01FF to 0x0208. Note the dummy read at step number 6. It is important to remember to make one dummy read when reading data after setting the Cursor Address register.

STEP # | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15
DB7~DB0 | 0A | FF | 0B | 01 | 0D | * | 44 | 45 | 4E | 53 | 49 | 54 | 52 | 4F | 4E
RS | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
R/W | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1

Note: Check Busy Flag (BF) before steps 1, 3, and 5. All values are hexadecimal.

8.10 Bit Clear and Bit Set Instructions

R/W | RS | DB7 | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DB0 | Function
0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | O | Bit Clear Instruction
0 | 0 | 0 | 0 | 0 | 0 | 0 | (NB-1) binary |  |  | Bit Address
0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | Bit Set Instruction
0 | 0 | 0 | 0 | 0 | 0 | 0 | (NB-1) binary |  |  | Bit Address

The Clear/Set Bit instructions reset/set 1 bit in a byte of VRAM data to 0 or 1, respectively. The position of the bit in a byte is defined by NB. NB=1 refers to the LSB, D0. NB=8 refers to the MSB, D7.

The Cursor Address is automatically incremented by +1 after execution of these instructions. For example; to clear bit D4 of address 0x01FF and set bits D1 and D6 of 0x0200 use the following sequence:

STEP # | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14
DB7~DB0 | 0A | FF | 0B | 01 | 0E | 04 | 0F | 01 | 0A | 00 | 0B | 02 | 0F | 06
RS | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0
R/W | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0

Note: Check Busy Flag (BF) before steps 1, 3, 5, 7, 9 and 11. All values are hexadecimal.

8.11 Read BUSY FLAG

R/W | RS | DB7 | DB6 | DB5 | DB4 | DB3 | DB2 | DB1 | DB0 | Function
1 | 1 | BF | * | * | * | * | * | * | * | Read BUSY FLAG

This instruction is used to check whether the HD61830(B) is in the BUSY state or not. The BUSY FLAG (BF) should be checked before initiating any instruction to the HD61830(B), except when data is written in the register (RS=1).

BF=1: HD61830(B) is BUSY
BF=0: HD61830(B) is not BUSY

Table 8.12: Busy Signal Timing

Function | BUSY
 | BUSY FLAG | Min. | Max.
Write Instruction (RS=1) | NOT SET | - | 1µs
Write Data (RS=0) | SET | tCL2 | 2 x tCL2
Read/Write VRAM | SET | 2 x tCL2 | (2 + HP)tCL2
BIT Set/Clear | SET | (2 + HP)tCL2 | 2(HP+1)tCL2

Note: A safety factor of 3 times the maximum BUSY time indicated above should be used if the Busy Flag is not polled by the MPU before each instruction is sent to the HD61830(B).