Encoding Real x86 Instructions
x86 Instructions Overview
x86 Instruction Format Reference
x86 Opcode Sizes
x86 ADD Instruction Opcode
Encoding x86 Instruction Operands, MOD-REG-R/M Byte
General-Purpose Registers
REG Field of the MOD-REG-R/M Byte
MOD R/M Byte and Addressing Modes
SIB (Scaled Index Byte) Layout
Scaled Indexed Addressing Mode
Examples
Encoding ADD Instruction Example
Encoding ADD CL, AL Instruction
Encoding ADD ECX, EAX Instruction
Encoding ADD EDX, DISPLACEMENT Instruction
Encoding ADD EDI, [EBX] Instruction
Encoding ADD EAX, [ ESI + disp8 ] Instruction
Encoding ADD EBX, [ EBP + disp32 ] Instruction
Encoding ADD EBP, [ disp32 + EAX*1 ] Instruction
Encoding ADD ECX, [ EBX + EDI*4 ] Instruction
Encoding ADD Immediate Instruction
Encoding Eight, Sixteen, and Thirty-Two Bit Operands
Encoding Sixteen Bit Operands
x86 Instruction Prefix Bytes
Alternate Encodings for Instructions
x86 Opcode Summary
MOD-REG-R/M Byte Summary
ISA Design Considerations
ISA Design Challenges
Intel Architecture Software Developer's Manual
Intel Instruction Set Reference (Volume2)
Chapter 3 of Intel Instruction Set Reference
Intel Reference Opcode Bytes
Intel Reference Opcode Bytes, Cont.
Intel Reference Opcode Bytes, Cont.
Intel Reference Opcode Bytes, Cont.
Intel Reference Opcode Bytes, Cont.
Intel Reference Opcode Bytes, Cont.
Intel Reference Instruction Column
X86-64 Instruction Encoding
General Overview
Registers
Legacy Prefixes
LOCK prefix
REPNE/REPNZ, REP and REPE/REPZ prefixes
CS, SS, DS, ES, FS and GS segment override prefixes
Branch taken/not taken prefixes
Operand-size and address-size override prefix
NASM
Opcode
Legacy opcodes
Mandatory prefix
REX prefix
Usage
Encoding
Opcode
VEX/XOP opcodes
Three byte VEX escape prefix
Three byte XOP escape prefix
Two byte VEX escape prefix
3DNow! opcodes
Fixed opcode
Immediate opcode byte
ModR/M and SIB bytes
ModR/M
16-bit addressing
32/64-bit addressing
RIP/EIP-relative addressing
SIB
32/64-bit addressing
Displacement
Immediate
See Also
External References