//-----------------------------------------------------------------------------
// File: FX2regs.h
// Contents: EZ-USB FX2 register declarations and bit mask definitions.
//
//-----------------------------------------------------------------------------
#ifndef FX2REGS_H /* Header Sentry */
#define FX2REGS_H
//-----------------------------------------------------------------------------
// FX2 Related Register Assignments
//-----------------------------------------------------------------------------
#define XBYTE ((BYTE volatile xdata*)0)
#define XWORD ((WORD volatile xdata*)0)
#define PBYTE ((BYTE volatile pdata*)0)
#define PWORD ((WORD volatile pdata*)0)
#define GPIF_WAVE_DATA (XBYTE[0xE400])
#define RES_WAVEDATA_END (XBYTE[0xE480])
#define CPUCS (PBYTE[0x00])
#define IFCONFIG (PBYTE[0x01])
#define PINFLAGSAB (PBYTE[0x02])
#define PINFLAGSCD (PBYTE[0x03])
#define FIFORESET (PBYTE[0x04])
#define BREAKPT (PBYTE[0x05])
#define BPADDR (PWORD[0x06/2])
#define BPADDRH (PBYTE[0x06])
#define BPADDRL (PBYTE[0x07])
#define UART230 (PBYTE[0x08])
#define FIFOPINPOLAR (PBYTE[0x09])
#define REVID (PBYTE[0x0A])
#define REVCTL (PBYTE[0x0B])
#define EP1OUTCFG (PBYTE[0x10])
#define EP1INCFG (PBYTE[0x11])
#define EP2CFG (PBYTE[0x12])
#define EP4CFG (PBYTE[0x13])
#define EP6CFG (PBYTE[0x14])
#define EP8CFG (PBYTE[0x15])
#define EP2FIFOCFG (PBYTE[0x18])
#define EP4FIFOCFG (PBYTE[0x19])
#define EP6FIFOCFG (PBYTE[0x1A])
#define EP8FIFOCFG (PBYTE[0x1B])
#define EP2AUTOINLENH (PBYTE[0x20])
#define EP2AUTOINLENL (PBYTE[0x21])
#define EP4AUTOINLENH (PBYTE[0x22])
#define EP4AUTOINLENL (PBYTE[0x23])
#define EP6AUTOINLENH (PBYTE[0x24])
#define EP6AUTOINLENL (PBYTE[0x25])
#define EP8AUTOINLENH (PBYTE[0x26])
#define EP8AUTOINLENL (PBYTE[0x27])
#define EP2FIFOPFH (PBYTE[0x30])
#define EP2FIFOPFL (PBYTE[0x31])
#define EP4FIFOPFH (PBYTE[0x32])
#define EP4FIFOPFL (PBYTE[0x33])
#define EP6FIFOPFH (PBYTE[0x34])
#define EP6FIFOPFL (PBYTE[0x35])
#define EP8FIFOPFH (PBYTE[0x36])
#define EP8FIFOPFL (PBYTE[0x37])
#define EP2ISOINPKTS (PBYTE[0x40])
#define EP4ISOINPKTS (PBYTE[0x41])
#define EP6ISOINPKTS (PBYTE[0x42])
#define EP8ISOINPKTS (PBYTE[0x43])
#define INPKTEND (PBYTE[0x48])
#define EP2FIFOIE (PBYTE[0x50])
#define EP2FIFOIRQ (PBYTE[0x51])
#define EP4FIFOIE (PBYTE[0x52])
#define EP4FIFOIRQ (PBYTE[0x53])
#define EP6FIFOIE (PBYTE[0x54])
#define EP6FIFOIRQ (PBYTE[0x55])
#define EP8FIFOIE (PBYTE[0x56])
#define EP8FIFOIRQ (PBYTE[0x57])
#define IBNIE (PBYTE[0x58])
#define IBNIRQ (PBYTE[0x59])
#define NAKIE (PBYTE[0x5A])
#define NAKIRQ (PBYTE[0x5B])
#define USBIE (PBYTE[0x5C])
#define USBIRQ (PBYTE[0x5D])
#define EPIE (PBYTE[0x5E])
#define EPIRQ (PBYTE[0x5F])
#define GPIFIE (PBYTE[0x60])
#define GPIFIRQ (PBYTE[0x61])
#define USBERRIE (PBYTE[0x62])
#define USBERRIRQ (PBYTE[0x63])
#define ERRCNTLIM (PBYTE[0x64])
#define CLRERRCNT (PBYTE[0x65])
#define INT2IVEC (PBYTE[0x66])
#define INT4IVEC (PBYTE[0x67])
#define INTSETUP (PBYTE[0x68])
#define PORTACFG (PBYTE[0x70])
#define PORTCCFG (PBYTE[0x71])
#define PORTECFG (PBYTE[0x72])
#define I2CS (PBYTE[0x78])
#define I2DAT (PBYTE[0x79])
#define I2CTL (PBYTE[0x7A])
#define XAUTODAT1 (PBYTE[0x7B])
#define XAUTODAT2 (PBYTE[0x7C])
#define USBCS (PBYTE[0x80])
#define SUSPEND (PBYTE[0x81])
#define WAKEUPCS (PBYTE[0x82])
#define TOGCTL (PBYTE[0x83])
#define USBFRAMEH (PBYTE[0x84])
#define USBFRAMEL (PBYTE[0x85])
#define MICROFRAME (PBYTE[0x86])
#define FNADDR (PBYTE[0x87])
#define EP0BCH (PBYTE[0x8A])
#define EP0BCL (PBYTE[0x8B])
#define EP1OUTBC (PBYTE[0x8D])
#define EP1INBC (PBYTE[0x8F])
#define EP2BC (PWORD[0x90/2])
#define EP2BCH (PBYTE[0x90])
#define EP2BCL (PBYTE[0x91])
#define EP4BCH (PBYTE[0x94])
#define EP4BCL (PBYTE[0x95])
#define EP6BCH (PBYTE[0x98])
#define EP6BCL (PBYTE[0x99])
#define EP8BCH (PBYTE[0x9C])
#define EP8BCL (PBYTE[0x9D])
#define EP0CS (PBYTE[0xA0])
#define EP1OUTCS (PBYTE[0xA1])
#define EP1INCS (PBYTE[0xA2])
#define EP2CS (PBYTE[0xA3])
#define EP4CS (PBYTE[0xA4])
#define EP6CS (PBYTE[0xA5])
#define EP8CS (PBYTE[0xA6])
#define EP2FIFOFLGS (PBYTE[0xA7])
#define EP4FIFOFLGS (PBYTE[0xA8])
#define EP6FIFOFLGS (PBYTE[0xA9])
#define EP8FIFOFLGS (PBYTE[0xAA])
#define EP2FIFOBCH (PBYTE[0xAB])
#define EP2FIFOBCL (PBYTE[0xAC])
#define EP4FIFOBCH (PBYTE[0xAD])
#define EP4FIFOBCL (PBYTE[0xAE])
#define EP6FIFOBCH (PBYTE[0xAF])
#define EP6FIFOBCL (PBYTE[0xB0])
#define EP8FIFOBCH (PBYTE[0xB1])
#define EP8FIFOBCL (PBYTE[0xB2])
#define SUDPTRH (PBYTE[0xB3])
#define SUDPTRL (PBYTE[0xB4])
#define SUDPTRCTL (PBYTE[0xB5])
#define GPIFWFSELECT (PBYTE[0xC0])
#define GPIFIDLECS (PBYTE[0xC1])
#define GPIFIDLECTL (PBYTE[0xC2])
#define GPIFCTLCFG (PBYTE[0xC3])
#define GPIFADRH (PBYTE[0xC4])
#define GPIFADRL (PBYTE[0xC5])
#define GPIFTCB3 (PBYTE[0xCE])
#define GPIFTCB2 (PBYTE[0xCF])
#define GPIFTCB1 (PBYTE[0xD0])
#define GPIFTCB0 (PBYTE[0xD1])
#define GPIFTCMSW (PWORD[0xCE/2])
#define GPIFTCLSW (PWORD[0xD0/2])
#define EP2GPIFFLGSEL (PBYTE[0xD2])
#define EP2GPIFPFSTOP (PBYTE[0xD3])
#define EP2GPIFTRIG (PBYTE[0xD4])
#define EP4GPIFFLGSEL (PBYTE[0xDA])
#define EP4GPIFPFSTOP (PBYTE[0xDB])
#define EP4GPIFTRIG (PBYTE[0xDC])
#define EP6GPIFFLGSEL (PBYTE[0xE2])
#define EP6GPIFPFSTOP (PBYTE[0xE3])
#define EP6GPIFTRIG (PBYTE[0xE4])
#define EP8GPIFFLGSEL (PBYTE[0xEA])
#define EP8GPIFPFSTOP (PBYTE[0xEB])
#define EP8GPIFTRIG (PBYTE[0xEC])
#define XGPIFSGLDATH (PBYTE[0xF0])
#define XGPIFSGLDATLX (PBYTE[0xF1])
#define XGPIFSGLDATLNOX (PBYTE[0xF2])
#define GPIFREADYCFG (PBYTE[0xF3])
#define GPIFREADYSTAT (PBYTE[0xF4])
#define GPIFABORT (PBYTE[0xF5])
#define FLOWSTATE (PBYTE[0xC6])
#define FLOWLOGIC (PBYTE[0xC7])
#define FLOWEQ0CTL (PBYTE[0xC8])
#define FLOWEQ1CTL (PBYTE[0xC9])
#define FLOWHOLDOFF (PBYTE[0xCA])
#define FLOWSTB (PBYTE[0xCB])
#define FLOWSTBEDGE (PBYTE[0xCC])
#define FLOWSTBHPERIOD (PBYTE[0xCD])
#define GPIFHOLDAMOUNT (PBYTE[0x0C])
#define UDMACRCH (PBYTE[0x7D])
#define UDMACRCL (PBYTE[0x7E])
#define UDMACRCQUAL (PBYTE[0x7F])
#define DBUG (PBYTE[0xF8])
#define TESTCFG (PBYTE[0xF9])
#define USBTEST (PBYTE[0xFA])
#define CT1 (PBYTE[0xFB])
#define CT2 (PBYTE[0xFC])
#define CT3 (PBYTE[0xFD])
#define CT4 (PBYTE[0xFE])
#define SETUPDAT (PBYTE+0xB8)
#define EP0BUF (XBYTE+0xE740)
#define EP1OUTBUF (XBYTE+0xE780)
#define EP1INBUF (XBYTE+0xE7C0)
#define EP2FIFOBUF (XBYTE+0xF000)
#define EP4FIFOBUF (XBYTE+0xF400)
#define EP6FIFOBUF (XBYTE+0xF800)
#define EP8FIFOBUF (XBYTE+0xFC00)
/*-----------------------------------------------------------------------------
Special Function Registers (SFRs)
The byte registers and bits defined in the following list are based
on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
If you modify the register definitions below, please regenerate the file
"ezregs.inc" which includes the same basic information for assembly inclusion.
-----------------------------------------------------------------------------*/
#ifdef __SDCC
# define SFRBYTE(name,addr) __sfr __at(addr) name
# define SFRBIT(name,addr) __sbit __at(addr) name
#else
# define SFRBYTE(name,addr) sfr name = addr
# define SFRBIT(name,addr) sbit name = addr
#endif
SFRBYTE(IOA,0x80);
SFRBIT(PA0,0x80);
SFRBIT(PA1,0x81);
SFRBIT(PA2,0x82);
SFRBIT(PA3,0x83);
SFRBIT(PA4,0x84);
SFRBIT(PA5,0x85);
SFRBIT(PA6,0x86);
SFRBIT(PA7,0x87);
SFRBYTE(SP,0x81);
SFRBYTE(DPL,0x82);
SFRBYTE(DPH,0x83);
SFRBYTE(DPL1,0x84);
SFRBYTE(DPH1,0x85);
SFRBYTE(DPS,0x86);
/* DPS */
// sbit SEL = 0x86+0;
SFRBYTE(PCON,0x87); /* PCON */
//sbit IDLE = 0x87+0;
//sbit STOP = 0x87+1;
//sbit GF0 = 0x87+2;
//sbit GF1 = 0x87+3;
//sbit SMOD0 = 0x87+7;
SFRBYTE(TCON,0x88);
/* TCON */
SFRBIT(IT0,0x88);
SFRBIT(IE0,0x89);
SFRBIT(IT1,0x8A);
SFRBIT(IE1,0x8B);
SFRBIT(TR0,0x8C);
SFRBIT(TF0,0x8D);
SFRBIT(TR1,0x8E);
SFRBIT(TF1,0x8F);
SFRBYTE(TMOD,0x89);
/* TMOD */
//sbit M00 = 0x89+0;
//sbit M10 = 0x89+1;
//sbit CT0 = 0x89+2;
//sbit GATE0 = 0x89+3;
//sbit M01 = 0x89+4;
//sbit M11 = 0x89+5;
//sbit CT1 = 0x89+6;
//sbit GATE1 = 0x89+7;
SFRBYTE(TL0,0x8A);
SFRBYTE(TL1,0x8B);
SFRBYTE(TH0,0x8C);
SFRBYTE(TH1,0x8D);
SFRBYTE(CKCON,0x8E);
/* CKCON */
//sbit MD0 = 0x89+0;
//sbit MD1 = 0x89+1;
//sbit MD2 = 0x89+2;
//sbit T0M = 0x89+3;
//sbit T1M = 0x89+4;
//sbit T2M = 0x89+5;
SFRBYTE(SPC_FNC,0x8F); // Was WRS in Reg320
/* CKCON */
//sbit WRS = 0x8F+0;
SFRBYTE(IOB,0x90);
SFRBIT(PB0,0x90);
SFRBIT(PB1,0x91);
SFRBIT(PB2,0x92);
SFRBIT(PB3,0x93);
SFRBIT(PB4,0x94);
SFRBIT(PB5,0x95);
SFRBIT(PB6,0x96);
SFRBIT(PB7,0x97);
SFRBYTE(EXIF,0x91); // EXIF Bit Values differ from Reg320
/* EXIF */
#define bmUSBINT (1 << 4)
#define bmI2CINT (1 << 5)
#define bmIE4 (1 << 6)
#define bmIE5 (1 << 7)
SFRBYTE(MPAGE,0x92);
//SFRBYTE(_XPAGE,0x92); // for SDCC
SFRBYTE(SCON0,0x98);
/* SCON0 */
SFRBIT(RI,0x98);
SFRBIT(TI,0x99);
SFRBIT(RB8,0x9A);
SFRBIT(TB8,0x9B);
SFRBIT(REN,0x9C);
SFRBIT(SM2,0x9D);
SFRBIT(SM1,0x9E);
SFRBIT(SM0,0x9F);
SFRBYTE(SBUF0,0x99);
SFRBYTE(AUTOPTR1H,0x9A);
SFRBYTE(AUTOPTR1L,0x9B);
SFRBYTE(AUTOPTR2H,0x9D);
SFRBYTE(AUTOPTR2L,0x9E);
SFRBYTE(IOC,0xA0);
SFRBIT(PC0,0xa0);
SFRBIT(PC1,0xa1);
SFRBIT(PC2,0xa2);
SFRBIT(PC3,0xa3);
SFRBIT(PC4,0xa4);
SFRBIT(PC5,0xa5);
SFRBIT(PC6,0xa6);
SFRBIT(PC7,0xa7);
SFRBYTE(INT2CLR,0xA1);
SFRBYTE(INT4CLR,0xA2);
SFRBYTE(IE,0xA8);
/* IE */
SFRBIT(EX0,0xA8);
SFRBIT(ET0,0xA9);
SFRBIT(EX1,0xAA);
SFRBIT(ET1,0xAB);
SFRBIT(ES0,0xAC);
SFRBIT(ET2,0xAD);
SFRBIT(ES1,0xAE);
SFRBIT(EA,0xAF);
SFRBYTE(EP2468STAT,0xAA);
/* EP2468STAT */
//sbit EP2E = 0xAA+0;
//sbit EP2F = 0xAA+1;
//sbit EP4E = 0xAA+2;
//sbit EP4F = 0xAA+3;
//sbit EP6E = 0xAA+4;
//sbit EP6F = 0xAA+5;
//sbit EP8E = 0xAA+6;
//sbit EP8F = 0xAA+7;
SFRBYTE(EP24FIFOFLGS,0xAB);
SFRBYTE(EP68FIFOFLGS,0xAC);
SFRBYTE(AUTOPTRSETUP,0xAF);
/* AUTOPTRSETUP */
SFRBIT(EXTACC,0xAF+0);
SFRBIT(APTR1FZ,0xAF+1);
SFRBIT(APTR2FZ,0xAF+2);
SFRBYTE(IOD,0xB0);
SFRBIT(PD0,0xb0);
SFRBIT(PD1,0xb1);
SFRBIT(PD2,0xb2);
SFRBIT(PD3,0xb3);
SFRBIT(PD4,0xb4);
SFRBIT(PD5,0xb5);
SFRBIT(PD6,0xb6);
SFRBIT(PD7,0xb7);
SFRBYTE(IOE,0xB1);
SFRBYTE(OEA,0xB2);
SFRBYTE(OEB,0xB3);
SFRBYTE(OEC,0xB4);
SFRBYTE(OED,0xB5);
SFRBYTE(OEE,0xB6);
SFRBYTE(IP,0xB8);
/* IP */
SFRBIT(PX0,0xB8);
SFRBIT(PT0,0xB9);
SFRBIT(PX1,0xBA);
SFRBIT(PT1,0xBB);
SFRBIT(PS0,0xBC);
SFRBIT(PT2,0xBD);
SFRBIT(PS1,0xBE);
SFRBYTE(EP01STAT,0xBA);
#define bmEP1INBSY 0x04
#define bmEP1OUTBSY 0x02
#define bmEP0BSY 0x01
SFRBYTE(GPIFTRIG,0xBB);
SFRBYTE(GPIFSGLDATH,0xBD);
SFRBYTE(GPIFSGLDATLX,0xBE);
SFRBYTE(GPIFSGLDATLNOX,0xBF);
SFRBYTE(SCON1,0xC0);
/* SCON1 */
SFRBIT(RI1,0xC0);
SFRBIT(TI1,0xC1);
SFRBIT(RB81,0xC2);
SFRBIT(TB81,0xC3);
SFRBIT(REN1,0xC4);
SFRBIT(SM21,0xC5);
SFRBIT(SM11,0xC6);
SFRBIT(SM01,0xC7);
SFRBYTE(SBUF1,0xC1);
SFRBYTE(T2CON,0xC8);
/* T2CON */
SFRBIT(CP_RL2,0xC8);
SFRBIT(C_T2,0xC9);
SFRBIT(TR2,0xCA);
SFRBIT(EXEN2,0xCB);
SFRBIT(TCLK,0xCC);
SFRBIT(RCLK,0xCD);
SFRBIT(EXF2,0xCE);
SFRBIT(TF2,0xCF);
SFRBYTE(RCAP2L,0xCA);
SFRBYTE(RCAP2H,0xCB);
SFRBYTE(TL2,0xCC);
SFRBYTE(TH2,0xCD);
SFRBYTE(PSW,0xD0);
/* PSW */
SFRBIT(P,0xD0);
SFRBIT(FL,0xD1);
SFRBIT(OV,0xD2);
SFRBIT(RS0,0xD3);
SFRBIT(RS1,0xD4);
SFRBIT(F0,0xD5);
SFRBIT(AC,0xD6);
SFRBIT(CY,0xD7);
SFRBYTE(EICON,0xD8); // Was WDCON in DS80C320; Bit Values differ from Reg320
/* EICON */
SFRBIT(INT6,0xDB);
SFRBIT(RESI,0xDC);
SFRBIT(ERESI,0xDD);
SFRBIT(SMOD1,0xDF);
SFRBYTE(ACC,0xE0);
SFRBYTE(EIE,0xE8); // EIE Bit Values differ from Reg320
/* EIE */
SFRBIT(EUSB,0xE8);
SFRBIT(EI2C,0xE9);
SFRBIT(EIEX4,0xEA);
SFRBIT(EIEX5,0xEB);
SFRBIT(EIEX6,0xEC);
SFRBYTE(B,0xF0);
SFRBYTE(EIP,0xF8); // EIP Bit Values differ from Reg320
/* EIP */
SFRBIT(PUSB,0xF8);
SFRBIT(PI2C,0xF9);
SFRBIT(EIPX4,0xFA);
SFRBIT(EIPX5,0xFB);
SFRBIT(EIPX6,0xFC);
#undef SFRBYTE
#undef SFRBIT
/*-----------------------------------------------------------------------------
Bit Masks
-----------------------------------------------------------------------------*/
/* CPU Control & Status Register (CPUCS) */
#define bmPRTCSTB bmBIT5
#define bmCLKSPD (bmBIT4 | bmBIT3)
#define bmCLKSPD1 bmBIT4
#define bmCLKSPD0 bmBIT3
#define bmCLKINV bmBIT2
#define bmCLKOE bmBIT1
#define bm8051RES bmBIT0
/* Port Alternate Configuration Registers */
/* Port A (PORTACFG) */
#define bmFLAGD bmBIT7
#define bmINT1 bmBIT1
#define bmINT0 bmBIT0
/* Port C (PORTCCFG) */
#define bmGPIFA7 bmBIT7
#define bmGPIFA6 bmBIT6
#define bmGPIFA5 bmBIT5
#define bmGPIFA4 bmBIT4
#define bmGPIFA3 bmBIT3
#define bmGPIFA2 bmBIT2
#define bmGPIFA1 bmBIT1
#define bmGPIFA0 bmBIT0
/* Port E (PORTECFG) */
#define bmGPIFA8 bmBIT7
#define bmT2EX bmBIT6
#define bmINT6 bmBIT5
#define bmRXD1OUT bmBIT4
#define bmRXD0OUT bmBIT3
#define bmT2OUT bmBIT2
#define bmT1OUT bmBIT1
#define bmT0OUT bmBIT0
/* I2C Control & Status Register (I2CS) */
#define bmSTART bmBIT7
#define bmSTOP bmBIT6
#define bmLASTRD bmBIT5
#define bmID (bmBIT4 | bmBIT3)
#define bmBERR bmBIT2
#define bmACK bmBIT1
#define bmDONE bmBIT0
/* I2C Control Register (I2CTL) */
#define bmSTOPIE bmBIT1
#define bm400KHZ bmBIT0
/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
#define bmIV4 bmBIT6
#define bmIV3 bmBIT5
#define bmIV2 bmBIT4
#define bmIV1 bmBIT3
#define bmIV0 bmBIT2
/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
#define bmEP0ACK bmBIT6
#define bmHSGRANT bmBIT5
#define bmURES bmBIT4
#define bmSUSP bmBIT3
#define bmSUTOK bmBIT2
#define bmSOF bmBIT1
#define bmSUDAV bmBIT0
/* Breakpoint register (BREAKPT) */
#define bmBREAK bmBIT3
#define bmBPPULSE bmBIT2
#define bmBPEN bmBIT1
/* Interrupt 2 & 4 Setup (INTSETUP) */
#define bmAV2EN bmBIT3
#define INT4IN bmBIT1
#define bmAV4EN bmBIT0
/* USB Control & Status Register (USBCS) */
#define bmHSM bmBIT7
#define bmDISCON bmBIT3
#define bmNOSYNSOF bmBIT2
#define bmRENUM bmBIT1
#define bmSIGRESUME bmBIT0
/* Wakeup Control and Status Register (WAKEUPCS) */
#define bmWU2 bmBIT7
#define bmWU bmBIT6
#define bmWU2POL bmBIT5
#define bmWUPOL bmBIT4
#define bmDPEN bmBIT2
#define bmWU2EN bmBIT1
#define bmWUEN bmBIT0
/* End Point 0 Control & Status Register (EP0CS) */
#define bmHSNAK bmBIT7
/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
#define bmEPBUSY bmBIT1
#define bmEPSTALL bmBIT0
/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
#define bmEPFULL bmBIT3
#define bmEPEMPTY bmBIT2
/* Endpoint Status (EP2468STAT) SFR bits */
#define bmEP8FULL bmBIT7
#define bmEP8EMPTY bmBIT6
#define bmEP6FULL bmBIT5
#define bmEP6EMPTY bmBIT4
#define bmEP4FULL bmBIT3
#define bmEP4EMPTY bmBIT2
#define bmEP2FULL bmBIT1
#define bmEP2EMPTY bmBIT0
/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
#define bmSDPAUTO bmBIT0
/* Endpoint Data Toggle Control (TOGCTL) */
#define bmQUERYTOGGLE bmBIT7
#define bmSETTOGGLE bmBIT6
#define bmRESETTOGGLE bmBIT5
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
#define bmEP8IBN bmBIT5
#define bmEP6IBN bmBIT4
#define bmEP4IBN bmBIT3
#define bmEP2IBN bmBIT2
#define bmEP1IBN bmBIT1
#define bmEP0IBN bmBIT0
/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
#define bmEP8PING bmBIT7
#define bmEP6PING bmBIT6
#define bmEP4PING bmBIT5
#define bmEP2PING bmBIT4
#define bmEP1PING bmBIT3
#define bmEP0PING bmBIT2
#define bmIBN bmBIT0
/* Interface Configuration bits (IFCONFIG) */
#define bmIFCLKSRC bmBIT7
#define bm3048MHZ bmBIT6
#define bmIFCLKOE bmBIT5
#define bmIFCLKPOL bmBIT4
#define bmASYNC bmBIT3
#define bmGSTATE bmBIT2
#define bmIFCFG1 bmBIT1
#define bmIFCFG0 bmBIT0
#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
#define bmIFGPIF bmIFCFG1
/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
#define bmINFM bmBIT6
#define bmOEP bmBIT5
#define bmAUTOOUT bmBIT4
#define bmAUTOIN bmBIT3
#define bmZEROLENIN bmBIT2
#define bmWORDWIDE bmBIT0
/* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specidic
features */
#define bmNOAUTOARM bmBIT1
#define bmSKIPCOMMIT bmBIT0
/* Fifo Reset bits (FIFORESET) */
#define bmNAKALL bmBIT7
#endif /* FX2REGS_H */
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