//-----------------------------------------------------------------------------
// File: atapi.h
// Contents: Header file
//
// Copyright (c) 1999 Cypress Semiconductor, Inc. All rights reserved
//
// $Archive: /USB/atapifx2/CY4611B/atapi.h $
// $Date: 6/26/05 1:57p $
// $Revision: 8 $
//-----------------------------------------------------------------------------
#ifndef ATAPI_H
#define ATAPI_H
// struct for storing mx2 config data
typedef struct
{
WORD Signature; // 0-1
BYTE ApmValue; // 2
BYTE AtaInitTimeout; // 3
BYTE AtaCommand; // 4
BYTE MiscConfig; // 5
//sbit bATA_UDMA_ENABLE = miscConfig^7; (copied)
//sbit bATAPI_UDMA_ENABLE = miscConfig^6; (copied)
//sbit bENABLE_WRITE_CACHE_MODE_PAGE= miscConfig^5;
//sbit bCOMPLIANCE_MODE = miscConfig^4; // Compliance mode uses the INTRQ pin less, but it will pass the BOT tests.
//sbit bWAIT_FOR_BUSY_BIT = miscConfig^3;
//sbit bSHORT_PACKET_BEFORE_STALL = miscConfig^2;
//sbit bSRST_ENABLE = miscConfig^1;
//sbit bSKIP_PIN_RESET = miscConfig^0;
BYTE UdmaConfig; // 6
BYTE PioConfig; // 7
BYTE PinConfig; // 8 Controls 100 pin package
//sbit bBUTTON_PINOUT = pinConfig ^ 7;
//sbit bATA_ENABLED = pinConfig ^ 6;
//sbit bBIG_PACKAGE = pinConfig ^ 5;
//sbit bATA_EN = pinConfig ^ 4;
//sbit bNewAt2pinout = pinConfig ^ 3;
//sbit bHS_INDICATOR = pinConfig ^ 2;
//sbit bDRVPWRVLD_POLARITY = pinConfig ^ 1;
//sbit bDRVPWRVLD_ENABLE = pinConfig ^ 0; (CF = 1)
BYTE GpioOE; // 9
BYTE GpioData; // A
BYTE Lun0String; // B
BYTE Lun1String; // C
BYTE delayAfterReset; // D
BYTE MiscConfig2; // E
//sbit bCF_USES_UDMA = MiscConfig2 ^ 3;
//sbit b2LUN_SET_BY_EEPROM = MiscConfig2 ^ 2;
//sbit b1LUN_SET_BY_EEPROM = MiscConfig2 ^ 1;
//sbit bSEARCH_ATA_ON_WAKEUP = MiscConfig2 ^ 0;
BYTE pad3; // F
} MX2_CONFIG_DATA;
// bit defines for mx2 config data
//#define ATA_UDMA_ENABLE 0x80
//#define ATAPI_UDMA_ENABLE 0x40
//#define WAIT_FOR_BUSY_BIT 0x08
//#define SHORT_PACKET_BEFORE_STALL 0x04
//#define SRST_ENABLE 0x02
//#define SKIP_PIN_RESET 0x01
///////////////////////////////////////////////////////////////////////////////
// Configuration Settings -- Additional settings beyond the command line
// parameters in the build options. The build option string is limited to 255
// characters, so many flags are here.
///////////////////////////////////////////////////////////////////////////////
// DEVICE_TYPE_IS_SCSI
// DEVICE_TYPE_IS_IDE -- Enable SCSI commands or IDE commands. SCSI commands
// are used by ATAPI devices. IDE devices are typically hard drives. Both
// of these flags may be active at once to support both types of devices. If
// one of these flags is disabled, it saves a significant amount of code space.
// All of the base code images support IDE. The CF only base image does NOT
// support SCSI, so that option is on the command line.
#define DEVICE_TYPE_IS_IDE TRUE
// APM_VALUE - ATA Device Automatic Power Management Value. If an attached ATA
// device supports APM and this field contains other than 0x00, the Initialization
// state machines will issue a SET FEATURES command to Enable APM with the register
// value during the drive initialization process. Setting APM Value to 0x00 disables
// this functionality. This register value is ignored with ATAPI devices.
#define APM_VALUE (mx2_config_data.ApmValue)
// ATA_INIT_TIMEOUT - Time in 128 millisecond granularity before the firmware
// stops polling the ALT STAT register for reset complete and restarts the reset
// process (0x80 = 16.4 seconds).
#define ATA_INIT_TIMEOUT (mx2_config_data.AtaInitTimeout)
// ATA_UDMA_ENABLE - Enable Ultra Mode data transfer support for ATA devices. If
// enabled, AND the ATA device reports UDMA support, the firmware will utilize
// UDMAdata transfers.
#define ATA_UDMA_ENABLE bATA_UDMA_ENABLE
// ATAPI_UDMA_ENABLE - Enable Ultra Mode data transfer support for ATAPI devices.
// If enabled,AND the ATAPI device reports UDMA support, the CY7C68200 will
// utilizeUDMA data transfers.
#define ATAPI_UDMA_ENABLE bATAPI_UDMA_ENABLE
// WAIT_FOR_BUSY_BIT - If set to TRUE, enables a delay of up to 120ms at each
// read of the DRQ bit where the device data length does not match the host data
// length. This allows the firmware to work with most devices that incorrectly
// clear the BUSY bit before a valid status is present.
#define WAIT_FOR_BUSY_BIT bWAIT_FOR_BUSY_BIT
// ATAPI_WAIT_FOR_SERV_BIT -- Wait for the SERV bit to become TRUE before trying the next
// ATAPI command. This switch forces the code to wait for both BSY = 0 and SERV = 1 before
// allowing an ATAPI command. Some drives require this (Mitsumi SR244W1). SERV=1 is not
// defined by the ATAPI spec and may produce unpredictable results. Recommended
// setting = FALSE.
#define ATAPI_WAIT_FOR_SERV_BIT FALSE
// SHORT_PACKET_BEFORE_STALL - Determines if a short packet is sent prior to
// the STALL ofan IN endpoint. The USB Mass Storage Class Bulk-Only
// Specification allows a device to send a short or zero-length IN packet
// prior to returning a STALL handshake for certain cases. Certain host
// controller drivers may require a short packet prior to STALL.
#define SHORT_PACKET_BEFORE_STALL bSHORT_PACKET_BEFORE_STALL
// SRST_ENABLE - If srt to TRUE, firmware will perform a SRST reset during
// drive initialization. Note: At least one reset must be en-abled.
// Do not set SRST to FALSE and Skip Pin Reset to TRUE at the
// same time.
#define SRST_ENABLE bSRST_ENABLE
// SKIP_PIN_RESET - Skip ATA_NRESET assertion. Note: SRST Enable must be
// set in conjunction with Skip Pin Reset. Setting this bit causes the
// firmware to bypass ARESET# during initialization. All reset events except
// a power-on reset utilize SRST as the drive mechanism.
//
// FALSE = Allow ARESET# assertion for all resets.
// TRUE = Disable ARESET# assertion except for power-on reset cycles.
#define SKIP_PIN_RESET bSKIP_PIN_RESET
// UDMA_MODES - These bits select which UDMA modes, if supported, are
// enabled. Setting to 1 enables. Multiple bits may be set. The
// firmware will operate in the highest enabled UDMA mode supported by
// the device.
//
// Recommended Setting: 0x14 (UDMA mode2 and mode4 only)
#define UDMA_MODES (mx2_config_data.UdmaConfig) /* 0x14 */
#define DMA_MODES (mx2_config_data.PioConfig & 4)
// PIO_MODES - These bits select which PIO modes, if supported, are
// en-abled. Setting to 1 enables. Multiple bits may be set. The
// firmware will operate in the highest enabled PIO mode supported by
// the device. The firmware supports PIO modes 0, 3, and 4 only. PIO
// mode 0 is always enabled.
// Bit Descriptions
// 1 Enable PIO mode 4.
// 0 Enable PIO mode 3.
#define PIO_MODES (mx2_config_data.PioConfig & 3)
// ATA_ENABLED
// If this bit is set, the ATA bus will be checked for one or two active ATA devices
// on startup. If no device is found, we will never attach to the bus.
#define ATA_ENABLED (bATA_ENABLED)
// USE_ATA_DEVICE_SERIAL_NUMBER - For ATA devices, determines if the firmware
// uses the serial number reported by the device as the USB serial number.
// If TRUE, firmware uses the serial number reported by the device in
// response to IDENTIFY_DEVICE command. If FALSE, the firmware sets
// the USB serial number index to 0 (i.e. no serial number string is
// reported in the device descriptor).
//
// Recommended Setting: FALSE
#define USE_ATA_DEVICE_SERIAL_NUMBER FALSE
// USE_ATAPI_DEVICE_SERIAL_NUMBER - For ATAPI devices, determines
// if the firmware uses the serial number reported by the device as
// the USB serial number. If TRUE, firmware uses the serial number
// reported by the device in response to IDENTIFY_DEVICE command.
// If FALSE, the firmware sets the USB serial number index to 0
// (i.e. no serial number string is reported in the device descriptor).
// Many ATAPI devices do not report a unique serial number. It is
// better to report no serial number than to report a non-unique
// serial number.
//
// Recommended Setting: FALSE
#define USE_ATAPI_DEVICE_SERIAL_NUMBER FALSE
// NIBBLE_CONVERT_SERIAL_NUMBER - Determines if the firmware converts
// each nibble of the serial number reported by the device into a
// single character of the USB serial number. The Bulk-only mass
// storage class spec only allows HEX characters (0-9 and A-F) in the
// device serial number. Some devices report other ASCII characters.
// Converting each nibble into HEX assures spec compliance while
// maintaining the uniqueness of the serial number.
//
// Recommended Setting: FALSE
#define NIBBLE_CONVERT_SERIAL_NUMBER FALSE
//////////////////////////////////////////////////
// STANDBY_IMMEDIATE -- Enables special purpose power-saving code.
//
// Expected conditions:
// Self-powered, no bus-sharing, single IDE device
//
// This code will issue a standby_immediate command to the currently selected
// drive when a USB suspend condition is detected.
//
// This flag is set by the command line.
// #define STANDBY_IMMEDIATE TRUE
// DELAY_AFTER_RESET is the time (in milliseconds) that the firmware
// will pause after a ATA bus reset (soft or pin reset). Certain devices
// (in particular ATAPI devices in multi-LUN configurations) cannot be
// detected if they are accessed right after an ATA reset. This pause
// gives them time to recover from reset.
#define DELAY_AFTER_POWERUP 2000 /* This delay is recommended to allow for power stability before startup */
#define DELAY_AFTER_RESET 1000 /* */
// ATACB_ENABLE turns on support for the ATACB passthrough commands
#define ATACB_ENABLE TRUE
// struct for holding device info
typedef struct
{
BYTE NumCylindersMSB; // #Cyl MSB
BYTE NumCylindersLSB; // #Cyl LSB
BYTE NumHeads; // #Heads
BYTE NumSectPerTrack; // #SectorsPerTrack
BYTE MaxPIO;
BYTE udmaMode; // global to keep track of which udma mode we are in
BYTE commandSetSupport;
DWORD driveCapacity;
} DEVICE_CONFIG_DATA;
///////////////////////////////////////////////////////////////////////////////
// Interface specific function definitions
///////////////////////////////////////////////////////////////////////////////
void hardwareReset(void);
void writePIO8(char addr, BYTE indata);
void fastWritePIO8(char addr, BYTE indata);
void writePIO16(WORD count);
void readPIO16(WORD count);
BYTE readPIO8(char addr);
BYTE readATAPI_STATUS_REG(void);
BYTE readATAPI_ALT_STATUS_REG(void);
WORD readWordPIO8(char addr);
void initUdmaRead(void);
void initUdmaWrite(void);
void slowDownOnUDMAErrors(void);
void prepUDMA(BYTE b2, BYTE b1, BYTE b0);
void readUDMA(void);
void writeUDMA(void);
void abortGPIF(void);
void LoadandVerifyWaveForm(BYTE *WaveForm);
WORD getDriveDataLen(void);
void ResetAndArmEp2(void);
void configureATATransferMode(BYTE mode);
bit EEPROMWriteBlock(WORD addr, BYTE xdata * ptr, BYTE len);
bit EEPROMWrite(WORD len, WORD addr);
bit EEWaitForDone(void);
void waitForInBuffer(void);
//void detectSCSIvsATA(void);
void mymemmove(BYTE idata * dest, BYTE idata * src, BYTE len);
void SendDeviceIdentifyCommand(bit waitForINTRQ);
void FetchDeviceIdentifyIntoEp6(void);
BYTE checkCBW(void);
BYTE processATACB(void);
void loadEP6BC(WORD dataLen);
void EP6Manual(void);
void EP2Manual(void);
bit ATACBcheckStatus(void);
void enterMfgMode(void);
void setDefaultConfig(void);
void driveATABus(void);
void triStateATABus(void);
BYTE flushCache(void);
void standbyImmediate(void);
void initDriveAfterReset(void);
#define FAIL_IN_ON_TIMEOUT 1
#define DONT_FAIL_IN_ON_TIMEOUT 0
///////////////////////////////////////////////////////////////////////////////
// Common function definitions
///////////////////////////////////////////////////////////////////////////////
//------------ ide ------------------------------
void softReset(void);
void TD_Init(void);
void TD_Poll(void);
void SetupCommand(void);
void stallEP2OUT(void);
BYTE SCSITestUnitReady(void);
void resetATADevice(void);
void processCBWHeader(void);
void processCBW(void);
BYTE processConfigCBCommand(void);
void sendUSBS(BYTE passOrFail);
void sendRAMData(BYTE xdata *inData, WORD dataTransferLen);
BYTE generalSCSIInCommand(void);
BYTE generalSCSIOutCommand(void);
BYTE generalIDEInCommand(void);
BYTE generalIDEOutCommand(void);
void failedIn(void);
void ATAPIIdDevice(void);
bit waitForBusyBit(void);
void mymemmovexx(BYTE xdata * dest, BYTE xdata * src, WORD len);
void writeATA_DRIVESEL_REG(void);
void checkATAEnable(void);
void sendprev(void);
#if DEVICE_TYPE_IS_IDE
bit checkForMedia(bit commandProcessing);
#else
#define checkForMedia(x)
#endif
void mymemmoveix(BYTE idata * dest, BYTE xdata * src, BYTE len); //mdnspd
void fastReadStart(void);
bit fastReadComplete(void);
void fastWriteStart(void);
bit fastWriteComplete(void);
unsigned char mymemcmpa(unsigned char idata * s1, unsigned char xdata * s2, unsigned char len);
bit EEPROMRead(WORD addr, WORD length, BYTE xdata *buf);
void ATAInit(void);
BYTE scsiWriteUdma(void);
BYTE scsiReadUdma(void);
BYTE waitForDRQBit(bit expectedValue);
bit setFeatures(BYTE command, BYTE subcommand);
void preloadSCSIRegs(void);
void checkGPIOonPA3(void);
#define IGNORE_DRIVE_LEN 1
#define LISTEN_TO_DRIVE_LEN 0
#define BUFFER_SIZE 0xf0
extern DWORD dataTransferLen;
extern WORD wPacketSize;
extern bit phaseErrorState;
#define HID_SUPPORT 0
#define CSM_SUPPORT 0
extern code BYTE DeviceDscr[]; // as for all descriptors, length at offset 0
extern code BYTE DeviceQualDscr[];
extern code BYTE HIDReportDscr[];
#define HIDReportDscrLen 34
extern code BYTE FullSpeedConfigDscr[]; // here: full length at offset 2 (<256)
//#define FullSpeedConfigDscrLen (9+9+7+7+CSM_SUPPORT*(9+4+9+6)+HID_SUPPORT*(9+9)+7)
// inside FullSpeedConfigDscr:
#if CSM_SUPPORT
#define CSMIntrfcDscr (FullSpeedConfigDscr+9+9+7+7)
#define CSMGeneralDscr (CSMIntrfcDscr+CSM_SUPPORT*(9))
#define CSMChannelDscr (CSMIntrfcDscr+CSM_SUPPORT*(9+4))
#define CSMCSMDscr (CSMIntrfcDscr+CSM_SUPPORT*(9+4+9))
#endif
#if HID_SUPPORT
#define HIDIntrfcDscr (CSMIntrfcDscr+CSM_SUPPORT*(9+4+9+6))
#define HIDDscr (HIDIntrfcDscr+HID_SUPPORT*(9))
#endif
extern code BYTE StringDscr0[],StringDscr1[],StringDscr2[],StringDscr3[];
void powerOn();
void powerOff();
extern MX2_CONFIG_DATA xdata mx2_config_data;
extern bit bShortPacketSent;
//extern bit bExtAddrSupport;
extern bit mfgMode;
extern volatile BYTE AlternateSetting; // Alternate settings
extern volatile BYTE Configuration; // Current configuration
extern idata BYTE prevCmd[12];
extern bit attemptFastRead;
extern bit attemptFastWrite;
extern bit attemptFastScsi;
extern WORD gSectorcount;
extern idata DWORD prevDataTransferLen;
extern bit mfgMode;
extern char sensePtr;
extern const char code WaveDataPioUDMA[128+64];
extern BYTE intrfcSubClass;
extern BYTE udmaErrorCount;
extern volatile BYTE seconds;
extern volatile BYTE hertz61ticks;
// support for higher PIO modes
#define PIO4 0x02
#define PIO3 0x01
#define PIO_MODE1 0x09
#define PIO_MODE2 0x0A
#define PIO_MODE3 0x0B
#define PIO_MODE4 0x0C
#define dataTransferLenMSW ((WORD *) (&dataTransferLen))[0]
#define dataTransferLen23W ((WORD *) (&dataTransferLen2SB))[0]
#define dataTransferLenLSW ((WORD *) (&dataTransferLen))[1]
#define dataTransferLenMSB ((BYTE *) (&dataTransferLen))[0]
#define dataTransferLen2SB ((BYTE *) (&dataTransferLen))[1]
#define dataTransferLen3SB ((BYTE *) (&dataTransferLen))[2]
#define dataTransferLenLSB ((BYTE *) (&dataTransferLen))[3]
#define USBS_PASSED 0
#define USBS_FAILED 1
#define USBS_PHASE_ERROR 2
#define IN_MASS_STORAGE_CLASS_RESET (bmHSNAK & EP0CS && SETUPDAT[1] == 0xFF/*SC_MASS_STORAGE_RESET*/)
// Local defines from the mass storage class spec
#define CBW_TAG 4
#define CBW_DATA_TRANSFER_LEN_LSB 8
#define CBW_DATA_TRANSFER_LEN_MSB 9
#define CBW_FLAGS 12
#define CBW_FLAGS_DIR_BIT 0x80
#define CBW_LUN 13
#define CBW_CBW_LEN 14
#define CBW_CBW_LEN_MASK 0xf
#define CBW_DATA_START 15
// Cypress Vendor Specific Config CB defines
#define CONFIG_CB_COMMAND 0x24
#define CONFIG_CB_SUBCOMMAND_EEPROM_RW 0x26
#define CONFIG_CB_SUBCOMMAND_MFG 0x27
#define CONFIG_CB_SUBCOMMAND_OFFSET 0x10
#define CONFIG_CB_EEPROM_ADDR_LSB 0x13
#define ATACB_COMMAND 0x24
#define MX2_EEPROM_SIGNATURE 0x4D4D
#define AT2LP_EEPROM_SIGNATURE 0x534b
// Local defines for the mass storage device
#define PROCESS_CBW_TIMEOUT_RELOAD 0x7000
#define HS_BULK_PACKET_SIZE 0x200
#define FS_BULK_PACKET_SIZE 0x40
#define min(a,b) (((a)<(b))?(a):(b))
#define max(a,b) (((a)>(b))?(a):(b))
// Wait for the drive interrupt macro
#if REVC_4611_BOARD
#define WAIT_FOR_INTRQ() {if(!bCOMPLIANCE_MODE){WAKEUPCS = bmWU | bmWUEN; while((WAKEUPCS & 0x40)) {WAKEUPCS = bmWU | bmWUEN;}}}
#else // AT2LP_PINOUT
#define WAIT_FOR_INTRQ() {if(!bCOMPLIANCE_MODE){while (!(IOA & 1)) ; }}
#endif
#define VBUS_POWERED (VBUSPWRD && bBIG_PACKAGE || FullSpeedConfigDscr[8] > 2)
#define PIO_ADDR_COMMAND 7
#define PIO_ADDR_DATA 0
#define ATAPI_INTRQ (PINSA & 0x01)
#define ATAPI_STATUS_BUSY_BIT 0x80
// #define ATAPI_STATUS_DRDY_BIT 0x40 Don't use this bit! It's not set after an A0 command!
#define ATAPI_STATUS_DF_BIT 0x20
#define ATAPI_STATUS_DSC_BIT 0x10
#define ATAPI_STATUS_DRQ_BIT 0x08
#define ATAPI_STATUS_CORR_BIT 0x04
#define ATAPI_STATUS_INDEX_BIT 0x02
#define ATAPI_STATUS_ERROR_BIT 0x01
// Errors for WRITE DMA
#define ATAPI_ERROR_ICRC_BIT 0x80
#define ATAPI_ERROR_WP_BIT 0x40
#define ATAPI_ERROR_MEDIA_CHANGED_BIT 0x20
#define ATAPI_ERROR_ABRT_BIT 0x04
#define ATAPI_ERROR_NO_MEDIA_BIT 0x02
#define ATA_SECTOR_SIZE 0x200
#define IDE_COMMAND_ID_DEVICE 0xec
#define IDE_ID_SERIAL_LEN 20
#define IDE_ID_TOTAL_SECTORS_LSW 60*2
#define IDE_ID_TOTAL_SECTORS_MSW 61*2
#define IDE_ID_TOTAL_48_BIT_SECTORS_LSW 100*2
#define IDE_ID_TOTAL_48_BIT_SECTORS_2SW 101*2
#define IDE_ID_TOTAL_48_BIT_SECTORS_3SW 102*2
#define IDE_ID_TOTAL_48_BIT_SECTORS_MSW 103*2
#define ATAPI_INQUIRY_SERIAL 10*2
#define ATAPI_COMMAND_ID_DEVICE 0xa1
#define ATAPI_COMMAND_ATAPI_PACKET 0xa0
#define ATAPI_COMMAND_SOFT_RESET 0x08
#define ATAPI_COMMAND_CHECK_POWER 0xe5
#define ATAPI_COMMAND_EXEC_DIAG 0x90
#define ATAPI_COMMAND_IDLE 0xe3
#define ATAPI_COMMAND_IDLE_IMMED 0xe1
#define ATAPI_COMMAND_NOP 0x00
#define ATAPI_COMMAND_SERVICE 0xa2
#define ATAPI_COMMAND_SET_FEATURES 0xef
#define SET_FEATURES_WRITE_CACHE_DISABLE 0x82
#define SET_FEATURES_WRITE_CACHE_ENABLE 0x02
#define ATAPI_PACKET_LOAD_UNLOAD 0xa6
#define ATAPI_CONTROL_REG_SOFT_RESET 4
#define ATAPI_CONTROL_REG_DEFAULT 8
// Converted RBC commands
#define ATA_COMMAND_READ_10 0x20
#define ATA_COMMAND_READ_10_EXT 0x24
#define ATA_COMMAND_WRITE_10 0x30
#define ATA_COMMAND_WRITE_10_EXT 0x34
#define ATA_COMMAND_VERIFY_10 0x40
#define ATA_COMMAND_VERIFY_10_EXT 0x42
#define ATA_COMMAND_DMAREAD_RETRY 0xC8
#define ATA_COMMAND_DMAREAD_RETRY_EXT 0x25
// #define ATA_COMMAND_DMAREAD_NORETRY 0xC9 Obsolete in ATA-6
#define ATA_COMMAND_DMAWRITE_RETRY 0xCA
#define ATA_COMMAND_DMAWRITE_RETRY_EXT 0x35
// #define ATA_COMMAND_DMAWRITE_NORETRY 0xCB Obsolete in ATA-6
#define ATA_COMMAND_SEEK 0x70
#define ATA_COMMAND_MEDIA_LOCK 0xde
#define ATA_COMMAND_MEDIA_UNLOCK 0xdf
#define ATA_COMMAND_FLUSH_CACHE 0xe7
#define ATA_COMMAND_MEDIA_EJECT 0xed
#define ATA_COMMAND_STANDBY_IMMEDIATE 0xe0
#define ATA_COMMAND_SLEEP 0xe6
// Still unconverted RBC commands
#define ATA_COMMAND_INQUIRY 0x12
#define ATA_COMMAND_MODE_SELECT_6 0x15
#define ATA_COMMAND_MODE_SENSE_6 0x1A
#define ATA_COMMAND_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E
#define ATA_COMMAND_TEST_UNIT_READY 0x00
#define ATA_COMMAND_WRITE_BUFFER 0x3B
// Optional RBC commands
#define ATA_COMMAND_NOP 0x00
#define ATA_COMMAND_FORMAT_UNIT 0x04
#define ATA_COMMAND_PERSISTENT_RESERVE_IN 0x5E
#define ATA_COMMAND_PERSISTENT_RESERVE_OUT 0x5F
#define ATA_COMMAND_RELEASE_6 0x17
#define ATA_COMMAND_REQUEST_SENSE 0x03
#define ATA_COMMAND_RESERVE_6 0x16
#define ATA_COMMAND_SYNCHRONIZE_CACHE 0x35
// Fields in the INQUIRY
#define SCSI_INQUIRY_DEVICE_CLASS 0
#define SCSI_INQUIRY_REMOVABLE_BIT 0x80
#define SCSI_INQUIRY_REMOVABLE_BYTE 1
#define ATAPI_INQUIRY_REMOVABLE_BYTE 0
#define SCSI_INQUIRY_DATA_FORMAT 3
#define SCSI_INQUIRY_MANUFACTURER 8
#define ATAPI_INQUIRY_MANUFACTURER 27
#define SCSI_INQUIRY_MANUFACTURER_LEN 24
#define ATAPI_INQUIRY_REVISION 73
#define SCSI_INQUIRY_REVISION 32
#define SCSI_INQUIRY_REVISION_LEN 4
#define SCSI_IDENTIFY_LEN 44
// Fields in the structure returned by the IDENTIFY DEVICE (ECh) and
// IDENTIFY PACKET DEVICE (A1h) commands (BYTE offsets)
#define IDENTIFY_FIELD_VALIDITY 53*2
#define IDENTIFY_DMA_MODES 63*2
#define IDENTIFY_ADVANCED_PIO 64*2
#define IDENTIFY_48BIT_ADDRESSING 83*2
#define IDENTIFY_COMMAND_SET_SUPPORT 83*2
#define IDENTIFY_COMMAND_SET_ENABLED 86*2
#define IDENTIFY_UDMA_MODES 88*2
#define IDENTIFY_NUM_CYLINDERS_LSB 54*2
#define IDENTIFY_NUM_CYLINDERS_MSB IDENTIFY_NUM_CYLINDERS_LSB+1
#define IDENTIFY_NUM_HEADS 55*2
#define IDENTIFY_NUM_SECT_PER_TRACK 56*2
// DMA supported modes bits from IDENTIFY DEVICE
#define DMA_MODE0 0x01
#define DMA_MODE1 0x02
#define DMA_MODE2 0x04
// UDMA supported modes bits from IDENTIFY DEVICE
#define UDMA_MODE0 0x01
#define UDMA_MODE1 0x02
#define UDMA_MODE2 0x04
#define UDMA_MODE3 0x08
#define UDMA_MODE4 0x10
#define UDMA_MODE5 0x20
// Advanced Power Management support/enabled bit from IDENTIFY
#define APM_FEATURE 0x08
// SET FEATURE sub-command codes
#define SET_FEATURE_TRANSFER_MODE 0x03
#define SET_FEATURE_APM_ENABLE 0x05
// Transfer mode settings
#define TRANSFER_MODE_DEFAULT 0x00
#define TRANSFER_MODE_PIO1 0x09
#define TRANSFER_MODE_PIO2 0x0A
#define TRANSFER_MODE_PIO3 0x0B
#define TRANSFER_MODE_PIO4 0x0C
#define TRANSFER_MODE_DMA0 0x20
#define TRANSFER_MODE_DMA1 0x21
#define TRANSFER_MODE_DMA2 0x22
#define TRANSFER_MODE_UDMA0 0x40
#define TRANSFER_MODE_UDMA1 0x41
#define TRANSFER_MODE_UDMA2 0x42
#define TRANSFER_MODE_UDMA3 0x43
#define TRANSFER_MODE_UDMA4 0x44
#define TRANSFER_MODE_UDMA5 0x45
// Local ATAPI defines -- Command register block
#define ATAPI_DATA_REG (DA(0)|CS(2))
#define ATAPI_ERROR_REG (DA(1)|CS(2))
#define ATAPI_FEATURE_REG (DA(1)|CS(2))
#define ATAPI_INT_CAUSE_REG (DA(2)|CS(2))
#define ATAPI_BYTE_COUNT_LSB (DA(4)|CS(2))
#define ATAPI_BYTE_COUNT_MSB (DA(5)|CS(2))
#define ATAPI_DRIVESEL_REG (DA(6)|CS(2))
#define ATAPI_STATUS_REG (DA(7)|CS(2))
#define ATAPI_COMMAND_REG (DA(7)|CS(2))
#define ATAPI_NULL_REG (DA(7)|CS(3))
// Local ATAPI defines -- Control register block
#define ATAPI_ALT_STATUS_REG (DA(6)|CS(1))
#define ATAPI_CONTROL_REG (DA(6)|CS(1))
// IDE registers -- Overlay on the ATAPI register space
#define ATA_DATA_REG (DA(0)|CS(2))
#define ATA_ERROR_REG (DA(1)|CS(2))
#define ATA_SECTOR_COUNT_REG (DA(2)|CS(2))
#define ATA_LBA_LSB_REG (DA(3)|CS(2))
#define ATA_LBA_2SB_REG (DA(4)|CS(2))
#define ATA_LBA_MSB_REG (DA(5)|CS(2))
#define ATA_DRIVESEL_REG (DA(6)|CS(2))
#define ATA_COMMAND_REG (DA(7)|CS(2))
#define senseCRCError 0
#define senseInvalidFieldInCDB 1
#define senseOk 2
#define senseNoMedia 3
#define senseWriteFault 4
#define senseReadError 5
#define senseAddrNotFound 6
#define senseInvalidOpcode 7
#define senseInvalidLBA 8
#define senseInvalidParameter 9
#define senseCantEject 10
#define senseMediaChanged 11
#define senseDeviceReset 12
#define senseWriteProtected 13
#define EEPROM_ADDR 0x51
#define EEPROM_PAGE_SIZE 8
#define MAX_LUN 2
#define CONFIG_SPACE_START 0x3f00 /* start of config area in EEPROM */
#endif
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